1Mbit Versatile SPI/8-bit Parallel Bus SRAM
MacTuxLin
Posts: 821
http://www.vlsi.fi/?id=194
A ready peripheral for Prop-II ? Go get your samples today!
A ready peripheral for Prop-II ? Go get your samples today!
Comments
This can read and write 4 bits in parallel? Thats acually kind of cool I wonder how that compares to reading writing 4 or 8 chips in parallel.. it says there 36mhz mc's ram is only 20 and vga is 25mhz so this could be a nice video buffer id assume! Man I seriously just ordered a megabyte of this microchip sram!
Interesting, and along the lines of the QuadSPI part from Microchip.
The VS23S010 strangely has a slower READ speed, than Write speed ?
Commands look to always be singe-bit mode, so it always needs 32 clocks to Set Address.
Pattern mode is close to Video, but not quite - it seems to hint at dual port but not clear what application Pattern mode was build for ?
The outer page calls the VS23S010 a "Easy to use accessory devices for audio applications",and an inner page says "This feature significantly reduces the computing requirement of a microcontroller for applications that require periodic output from the memory, such as a video frame buffer." - but they seem to have no Video blanking, or flyback-pause on Scan.
An 8 bit fast Video read, via a RAM-Palette, would have been interesting.
@jmg im sorta confused im sure u can clear this up, microchip has the quad spi mode but its former chip did not. both mc parts are 20mhz so exactly how are the new chips faster if limitedd to the same bandwith? do you think an 8 or even better 32 chip array in parallel is fast enough for video and decent xmm speeds?
The CLK speeds are nominally the same, but the new parts can enter Quad mode during the address phase, and so load an Address in 8 clocks, instead of 32.
Data pumping also occurs at 4 bits per clock, so the Data bandwidth is 4x faster.
Yes, more chips gives higher bandwidths, but at some stage you need to decide on Pin-Usage.
The VLSI part has some higher MHz rates, but always runs the ADR preamble in x1 mode, so random access of small data will be slower than MicroChip.
VLSI must have some large customer with a specific need for that device, as it is a little unusual.
i guess my thinking is if the mc parts are 4x faster than pulling the data and buffering it should drive vga that would effectively be like 80mhz minus prop overhead
Was thinking more about those many Prop-II pins.
Yeah, I'll sure try that out in quad SPI mode with Prop when I get the the samples
Depends what you mean by VGA.
Lowest std VGA clock speed is 25+MHz, and there are 32MHz and 40MHz rates too, up to 150MHz+.
So you might push a MicroChip part to 25MHz, but if you wanted 40Mhz then a 2:1 MUX would be needed, which somewhat negates the appeal of SPI devices.
The VLSI part is vague in vital areas. If you CAN use SPI to write to any location while Pattern reads, then it is Dual-Port, and that solves one problem with Video Buffering.
MCLK is 48MHz, but Pixel rate is MCLK/2/4/8, so you can do 24MHz Nibbles max, and then they suggest some jitter in starting, which is NOT good for Video : "5 − 7 MCLK cycles" ?!
It seems their customer is Audio, not Video, so this is unproven ground.
Now that's what I call service! If only more chip companies were this responsive.
-Phil
Yes, impressive response, but rather confirms they have not had Video on their Radar, and still no mention of if it is Dual port.
The suggestion of using the Streamed Data for Sync, also side-steps the start-jitter issue in their spec, but at considerable wasted RAM cost.
Eexxcellent! [in my best Mr. Burns voice]
-Phil
We'll see what transpires. Needless to say, I'm probably on their s---list for any further technical assistance. Oh, well.
-Phil
No.. No puppies please..
Jeff
-Phil
I guess some will now understand why I am wary of asking for free samples in Taiwan. They do ask for at least a major credit card to cover shipping.
Anyone playing with these yet? I'm getting ready to solder one up.
Jeff
It's been a while, but I'd just like to mention that we're finally in production with the VS23S010D-L, which is focused on PAL/NTSC video generation (though I have made a simple VGA demo too). I wrote a lengthy article about it in the Uzebox forum, at http://uzebox.org/forums/viewtopic.php?f=1&t=1754#p17111 .
8-bit Palette Test
What we now have is the VS23S010D-L chip getting in production, that has an integrated video DAC, 128 kilobytes of SRAM, any amount of which can be assigned to be video memory, xtal oscillator, internal PLL clock multiplexer, digital PAL/NTSC modulator and the necessary counters and logic to get bits from the SRAM and into the modulator. It's a bit more fancy that what I first conceived, but much more flexible. You can set the start address of pixel data for each line separately so you can duplicate lines and create horizontal/vertical scrolling effects. And you can have many different prototypes for a line - those are what forms the sync, burst and background areas. You can select the number of bits you want for the color components, from 1 to 20 bits per pixel. Obviously you can set the length of lines, number of lines and the resolution. There's even a block copy engine.
VS23S010 Forum at VLSI
VS23S010 Product Page
--
I have a slightly red face now when I read about the awful shipping cost experience described here. It's like a Homer Simpson "Doh" moment... I'm really sorry about it - I can just try to offer a point of view that might explain something.. We're talking about numbered chips here. That's the first of the first of the first units of a new IC that we get. The cost is something like USD100K or USD200K (depending on which costs you calculate in) and we get something like 50 to 80 of them. That's like 2000 dollars each. So if the sample order is accompanied with a shipper account ID, we happily take it as a courtesy, signaling that the receiver appreciates the samples enough to pay for the delivery. We'd probably not even give it another thought. And these chips, they've traveled across the world, each spent hours in the laboratory with engineers testing them by hand - of course we use the most secure and most expensive transport. For us it's a given. But of course, from your point of view it's different - you'd perhaps not even realize how precious these very early samples are. But we send them out happily - an early adopter gives the most valuable feedback for a new product.
So, I hope you guys can forgive us for this blunder. The guy at VLSI receiving the shipping bill back probably just thought that the chips had cost USD10K so why is he complaining about a couple hundred and thus had no idea what had just transpired and probably more than anything just was annoyed by having to do the paperwork. Well, that's life. I am sorry about it.
Well, at least finally.. Hehehe... knowing the guy who processed the shipping and knowing the guy who wrote this - it just puts a smile on my face. Oh, the happy days at the office.
Ok, so, this was just to let you know, that the awesome new composite video controller has arrived - in year 2016 no less. If only we'd had this in 1986!
-Panu
Wow, this is significant- I think this needs a new thread...
What price are these parts, and who stocks (will stock) them ?
You mention VS23S010D-L, which sounds like a Rev D, as the ~ 1 year older Web site mentions only VS23S010C ?
Data is VS23S010C, also 1 year old, and prelim, do you have confirmed MHz figures, for Vcc choices ? - and new data sheets ?
Those figures come from the test program, e.g. we run qualification in parallel (1000 hours, 125 degrees C) and then based on that qualification data we try to find the error mechanisms and set the test rejection limits for the production and those rejection limits, adjusted by chip aging profile, are what gets printed in the datasheet. I'm not sure how near the end of this process we are. It's not my project, actually, those guys at quality@vlsi.fi are a different breed of engineers... they take their time before they drop the "Preliminary" from the datasheet.
Do you have a specific question or a specific operation point in mind; I could ask the engineers about it.
The front page of the Jan 2015 data says
– Up to 36 MHz for SPI
– 15 MHz for 8-bit parallel interface
but further in, it gives other info
SPI clock frequency (read)
12 MHz VDD = 1.5 V
18 MHz VDD = 1.8 V
33 MHz VDD = 3.0 V
36 MHz ( @ 3.3 ?)
SPI clock frequency (write)
27 MHz VDD = 1.5 V
27 MHz VDD = 1.8 V
48 MHz VDD = 3.0 V
48 MHz
Clock frequency F XRD _ XWR
6 MHz VDD = 1.5 V
9 MHz VDD = 1.8 V
15 MHz VDD = 3.0 V
15 MHz
Clock frequency F XRD _ XWR
24 MHz VDD = 1.5 V
24 MHz VDD = 1.8 V
30 MHz VDD = 3.0 V
30 MHz
Why is read speed lower than write, is that allowing some Tsu on the host size ?
If you stream as in Video-Quad mode, there is no Tsu, so does read MHz then become the same as write MHz ?
A Prop1 can generate a read CLK of 40MHz or 48MHz (80 MHz or 96MHz SysCLK), plus lower, so those are obvious targets.
Package are shown as SO8 and TQFP48.
Are any other packages planned - eg TSSOP8 ?
There is also 4 x Analog mapping tagged :
1) Not connected in first prototypes, reserved for use in future Multi-IC VS23S010C-Ls.
Do those multi-ic versions still exist, and with what part codes ?
Some general answers now, some answers after I've asked the chip engineer.
- Reading is slower than writing, because there must be time for the data to arrive from the memory array to the shift register after the last bit of the address, once every 32 bits. When writing, bits can be happily banged to the shifter and internally there's plenty of time to write the data into the memory array.
- When video mode is active, some parts of the chip (internally) switch from being asynchronous to synchronous with the video clock, changing some timings.
- I can't quite put my finger on what you mean by "Video-Quad mode", but your timing questions seem very interesting. Can you rephrase those questions, pointing to specific pages and figures on the datasheet which are unclear.
- No multi-ic currently exists. Perhaps we ought to take that away from the datasheet so that people will not wait for it...
When used on 4 bit VGA, you would play back in Quad Read, at the Pixel clock rate.
There is mention of modes like StFastWV, but it is not clear if that is only for 48 pin part, and only Composite ?
ie can 8 pin Memory use some scan-playback, or must the host update start-address every line (that looks to cost 16 SysCLKs per scan line ?)
The Table on page 37 suggests all those modes are supported ? - but the Fig 26 only has Chroma YUV pathways ?
Bean