More cache driver build issues
average joe
Posts: 795
Well, I'm doing something wrong but not sure what. I'm not going to "blow-up" the board trying to figure this out. I'm just looking for a sanity check...
Test results are
' input parameters to rd_cache_line and wr_cache_line
vmaddr long 0 ' external address
hubaddr long 0 ' hub memory address
ptr long 0
count long 0 ' copy line size from shifted line size
'----------------------------------------------------------------------------------------------------
'
' !!!StartTouchburger Code here!!!
''' +-----------------------------------------------------------------------------------------------+
'' | Touchblade 161 Ram Driver (with grateful acknowlegements to Cluso and Average Joe) |
'' +-----------------------------------------------------------------------------------------------+
set161 mov count, line_size ' make a copy of line_size AND.
mov ptr, hubaddr ' hubaddr = hub page address
or outa,maskP16P20 ' set control pins high
or dira,maskP0P20 '%00000000_00011111_11111111_11111111
or outa,maskP22 ' pin 22 high
or dira,maskP22 ' and now set as an output
and outa,maskP0P8low ' P0-P7 low
or outa,#%11111110 ' group 1, displays all off
or outa,maskP8 ' P8 high, clocks out data
andn outa,maskP22 ' pin 22 low
and outa,maskP0P18low '%11111111_11111000_00000000_00000000
shr vmaddr, #1 ' schematic connects SRAM A0 to A0, not A1 - jsd
or outa,vmaddr ' send out ramaddr
andn outa,maskP20 ' clock low
andn outa,maskP19 ' load low
or outa,maskP20 ' clock high
or outa,maskP16P20 ' set control pins high
or outa,maskP22 ' pin 22 high
and outa,maskP0P8low ' P0-P7 low
or outa,#%11111101 ' group 2, displays all off
or outa,maskP8 ' P8 high, clocks out data
andn outa,maskP22 ' pin 22 low
set161_ret ret
'----------------------------------------------------------------------------------------------------
'
' rd_cache_line - read a cache line from external memory
'
' vmaddr is the external memory address to read
' hubaddr is the hub memory address to write
' line_size is the number of bytes to read
'
'----------------------------------------------------------------------------------------------------
rd_cache_line
' command T
pasmramtohub call #set161 ' get hubaddr,ramaddr,len and set control pins
and dira,maskP16P31 '%11111111_11111111_00000000_00000000 inputs
andn outa,maskP16 ' memory /rd low
ramtohub_loop mov data_16,ina ' get the data
wrword data_16,hubaddr ' move data to hub
andn outa,maskP20 ' clock 161 low
or outa,maskP20 ' clock 161 high
add ptr,#2 ' increment the hub address
djnz count,#ramtohub_loop
or outa,maskP16 ' memory /rd high
'mov latchvalue,#%11111111 ' all off
'call #set373 ' send out to the latch
and dira,maskP0P20low '%11111111_11100000_00000000_00000000
'andn dira,maskP22 ' and now set as an input
rd_cache_line_ret ret
'----------------------------------------------------------------------------------------------------
'
' wr_cache_line - write a cache line to external memory
'
' vmaddr is the external memory address to write
' hubaddr is the hub memory address to read
' line_size is the number of bytes to write
'
'----------------------------------------------------------------------------------------------------
wr_cache_line
' command S
pasmhubtoram call #set161 ' get hubaddr,ramaddr,len and set control pins
or dira,maskP0P15 ' %00000000_00000000_11111111_11111111 ' data bus outputs
hubtoram_loop and outa,maskP16P31 '%11111111_11111111_00000000_00000000 ' clear for output
rdword data_16,hubaddr ' get the word from hub
and data_16,maskP0P15 ' mask to a word only
or outa,data_16 ' send out the byte to P0-P15
andn outa,maskP17 ' set mem write low
add ptr,#2 ' increment by 2 bytes = 1 word. Put this here for small delay while writes
or outa,maskP17 ' mem write high
andn outa,maskP20 ' clock 161 low
or outa,maskP20 ' clock 161 high
djnz count,#hubtoram_loop ' loop this many times
'mov latchvalue,#%11111111 ' all off
'call #set373 ' send out to the latch
and dira,maskP0P20low '%11111111_11100000_00000000_00000000
'andn dira,maskP22 ' and now set as an input
wr_cache_line_ret ret
' variables
pasm_n long 0 ' general purpose value
data_16 long 0 ' general purpose value
' constants
slow_timing long %00000000_10000000_00000000_00000000
maskP0P2low long %11111111_11111111_11111111_11111000 ' P0-P2 low
maskP0P20 long %00000000_00011111_11111111_11111111 ' P0-P18 enabled for output plus P19,P20
maskP0P18low long %11111111_11111000_00000000_00000000 ' P0-P18 low
maskP16 long %00000000_00000001_00000000_00000000 ' pin 16
maskP17 long %00000000_00000010_00000000_00000000 ' pin 17
maskP18 long %00000000_00000100_00000000_00000000 ' pin 18
maskP19 long %00000000_00001000_00000000_00000000 ' pin 19
maskP20 long %00000000_00010000_00000000_00000000 ' pin 20
maskP22 long %00000000_01000000_00000000_00000000 ' pin 22
maskP16P31 long %11111111_11111111_00000000_00000000 ' pin 16 to pin 31
maskP0P15 long %00000000_00000000_11111111_11111111 ' for masking words
maskP16P20 long %00000000_00011111_00000000_00000000
maskP0P20low long %11111111_11100000_00000000_00000000 ' for returning all group pins HiZ
maskP16P17P20 long %00000000_00010011_00000000_00000000
maskP0P8low long %11111111_11111111_11111110_00000000 ' P0-P7 low
maskP8 long %00000000_00000000_00000001_00000000 ' pin 8
latchvalue long %00000000_00000000_00000000_00000000 ' current 373 value
Test results are
Test 0 Address Walking 0's 15 address bits. 00007ff8 00000000 00007ff4 00000000 00007fec 00000000 00007fdc 00000000 00007fbc 00000000 00007f7c 00000000 00007efc 00000000 00007dfc 00000000 00007bfc 00000000 000077fc 00000000 00006ffc 00000000 00005ffc 00002000 ERROR! Expected 0 @ 00007ffc after write to address 00005ffc 00002000 Test 1 Address Walking 1's 15 address bits. 00000004 00000000 00000008 00000000 00000010 00000000 00000020 00000000 00000040 00000000 00000080 00000000 00000100 00000000 00000200 00000000 00000400 00000000 00000800 00000000 00001000 00000000 00002000 00000000 00004000 00000000 Incremental Pattern Test 32 KB ---------------------------------------------------------------- wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww r ERROR at $00000000 Expected $00000001 Received $00000021 Address $00000000 0K Page Cache Dump TAG TAGVAL : Cache Line 000 00000000: 00000021 00001802 00001803 00001804 00001805 00001806 00001807 00001808 000 00000008: 00001809 0000180a 0000180b 0000180c 0000180d 0000180e 0000180f 00001810 000 00000010: 00001811 00001812 00001813 00001814 00001815 00001816 00001817 00001818 000 00000018: 00001819 0000181a 0000181b 0000181c 0000181d 0000181e 0000181f 00001820 001 00000020: 00001821 00001822 00001823 00001824 00001825 00001826 00001827 00001828 001 00000028: 00001829 0000182a 0000182b 0000182c 0000182d 0000182e 0000182f 00001830 001 00000030: 00001831 00001832 00001833 00001834 00001835 00001836 00001837 00001838 001 00000038: 00001839 0000183a 0000183b 0000183c 0000183d 0000183e 0000183f 00001840 002 00000040: 00001841 00001842 00001843 00001844 00001845 00001846 00001847 00001848 002 00000048: 00001849 0000184a 0000184b 0000184c 0000184d 0000184e 0000184f 00001850 002 00000050: 00001851 00001852 00001853 00001854 00001855 00001856 00001857 00001858 002 00000058: 00001859 0000185a 0000185b 0000185c 0000185d 0000185e 0000185f 00001860 003 00000060: 00001861 00001862 00001863 00001864 00001865 00001866 00001867 00001868 003 00000068: 00001869 0000186a 0000186b 0000186c 0000186d 0000186e 0000186f 00001870 003 00000070: 00001871 00001872 00001873 00001874 00001875 00001876 00001877 00001878 003 00000078: 00001879 0000187a 0000187b 0000187c 0000187d 0000187e 0000187f 00001880 004 00000080: 00001881 00001882 00001883 00001884 00001885 00001886 00001887 00001888 004 00000088: 00001889 0000188a 0000188b 0000188c 0000188d 0000188e 0000188f 00001890 004 00000090: 00001891 00001892 00001893 00001894 00001895 00001896 00001897 00001898 004 00000098: 00001899 0000189a 0000189b 0000189c 0000189d 0000189e 0000189f 000018a0 005 000000a0: 000018a1 000018a2 000018a3 000018a4 000018a5 000018a6 000018a7 000018a8 005 000000a8: 000018a9 000018aa 000018ab 000018ac 000018ad 000018ae 000018af 000018b0 005 000000b0: 000018b1 000018b2 000018b3 000018b4 000018b5 000018b6 000018b7 000018b8 005 000000b8: 000018b9 000018ba 000018bb 000018bc 000018bd 000018be 000018bf 000018c0 006 000000c0: 000018c1 000018c2 000018c3 000018c4 000018c5 000018c6 000018c7 000018c8 006 000000c8: 000018c9 000018ca 000018cb 000018cc 000018cd 000018ce 000018cf 000018d0 006 000000d0: 000018d1 000018d2 000018d3 000018d4 000018d5 000018d6 000018d7 000018d8 006 000000d8: 000018d9 000018da 000018db 000018dc 000018dd 000018de 000018df 000018e0 007 000000e0: 000018e1 000018e2 000018e3 000018e4 000018e5 000018e6 000018e7 000018e8 007 000000e8: 000018e9 000018ea 000018eb 000018ec 000018ed 000018ee 000018ef 000018f0 007 000000f0: 000018f1 000018f2 000018f3 000018f4 000018f5 000018f6 000018f7 000018f8 007 000000f8: 000018f9 000018fa 000018fb 000018fc 000018fd 000018fe 000018ff 00001900 008 00000100: 00001901 00001902 00001903 00001904 00001905 00001906 00001907 00001908 008 00000108: 00001909 0000190a 0000190b 0000190c 0000190d 0000190e 0000190f 00001910 008 00000110: 00001911 00001912 00001913 00001914 00001915 00001916 00001917 00001918 008 00000118: 00001919 0000191a 0000191b 0000191c 0000191d 0000191e 0000191f 00001920 009 00000120: 00001921 00001922 00001923 00001924 00001925 00001926 00001927 00001928 009 00000128: 00001929 0000192a 0000192b 0000192c 0000192d 0000192e 0000192f 00001930 009 00000130: 00001931 00001932 00001933 00001934 00001935 00001936 00001937 00001938 009 00000138: 00001939 0000193a 0000193b 0000193c 0000193d 0000193e 0000193f 00001940 00a 00000140: 00001941 00001942 00001943 00001944 00001945 00001946 00001947 00001948 00a 00000148: 00001949 0000194a 0000194b 0000194c 0000194d 0000194e 0000194f 00001950 00a 00000150: 00001951 00001952 00001953 00001954 00001955 00001956 00001957 00001958 00a 00000158: 00001959 0000195a 0000195b 0000195c 0000195d 0000195e 0000195f 00001960 00b 00000160: 00001961 00001962 00001963 00001964 00001965 00001966 00001967 00001968 00b 00000168: 00001969 0000196a 0000196b 0000196c 0000196d 0000196e 0000196f 00001970 00b 00000170: 00001971 00001972 00001973 00001974 00001975 00001976 00001977 00001978 00b 00000178: 00001979 0000197a 0000197b 0000197c 0000197d 0000197e 0000197f 00001980 00c 00000180: 00001981 00001982 00001983 00001984 00001985 00001986 00001987 00001988 00c 00000188: 00001989 0000198a 0000198b 0000198c 0000198d 0000198e 0000198f 00001990 00c 00000190: 00001991 00001992 00001993 00001994 00001995 00001996 00001997 00001998 00c 00000198: 00001999 0000199a 0000199b 0000199c 0000199d 0000199e 0000199f 000019a0 00d 000001a0: 000019a1 000019a2 000019a3 000019a4 000019a5 000019a6 000019a7 000019a8 00d 000001a8: 000019a9 000019aa 000019ab 000019ac 000019ad 000019ae 000019af 000019b0 00d 000001b0: 000019b1 000019b2 000019b3 000019b4 000019b5 000019b6 000019b7 000019b8 00d 000001b8: 000019b9 000019ba 000019bb 000019bc 000019bd 000019be 000019bf 000019c0 00e 000001c0: 000019c1 000019c2 000019c3 000019c4 000019c5 000019c6 000019c7 000019c8 00e 000001c8: 000019c9 000019ca 000019cb 000019cc 000019cd 000019ce 000019cf 000019d0 00e 000001d0: 000019d1 000019d2 000019d3 000019d4 000019d5 000019d6 000019d7 000019d8 00e 000001d8: 000019d9 000019da 000019db 000019dc 000019dd 000019de 000019df 000019e0 00f 000001e0: 000019e1 000019e2 000019e3 000019e4 000019e5 000019e6 000019e7 000019e8 00f 000001e8: 000019e9 000019ea 000019eb 000019ec 000019ed 000019ee 000019ef 000019f0 00f 000001f0: 000019f1 000019f2 000019f3 000019f4 000019f5 000019f6 000019f7 000019f8 00f 000001f8: 000019f9 000019fa 000019fb 000019fc 000019fd 000019fe 000019ff 00001a00 010 00000200: 00001a01 00001a02 00001a03 00001a04 00001a05 00001a06 00001a07 00001a08 010 00000208: 00001a09 00001a0a 00001a0b 00001a0c 00001a0d 00001a0e 00001a0f 00001a10 010 00000210: 00001a11 00001a12 00001a13 00001a14 00001a15 00001a16 00001a17 00001a18 010 00000218: 00001a19 00001a1a 00001a1b 00001a1c 00001a1d 00001a1e 00001a1f 00001a20 011 00000220: 00001a21 00001a22 00001a23 00001a24 00001a25 00001a26 00001a27 00001a28 011 00000228: 00001a29 00001a2a 00001a2b 00001a2c 00001a2d 00001a2e 00001a2f 00001a30 011 00000230: 00001a31 00001a32 00001a33 00001a34 00001a35 00001a36 00001a37 00001a38 011 00000238: 00001a39 00001a3a 00001a3b 00001a3c 00001a3d 00001a3e 00001a3f 00001a40 012 00000240: 00001a41 00001a42 00001a43 00001a44 00001a45 00001a46 00001a47 00001a48 012 00000248: 00001a49 00001a4a 00001a4b 00001a4c 00001a4d 00001a4e 00001a4f 00001a50 012 00000250: 00001a51 00001a52 00001a53 00001a54 00001a55 00001a56 00001a57 00001a58 012 00000258: 00001a59 00001a5a 00001a5b 00001a5c 00001a5d 00001a5e 00001a5f 00001a60 013 00000260: 00001a61 00001a62 00001a63 00001a64 00001a65 00001a66 00001a67 00001a68 013 00000268: 00001a69 00001a6a 00001a6b 00001a6c 00001a6d 00001a6e 00001a6f 00001a70 013 00000270: 00001a71 00001a72 00001a73 00001a74 00001a75 00001a76 00001a77 00001a78 013 00000278: 00001a79 00001a7a 00001a7b 00001a7c 00001a7d 00001a7e 00001a7f 00001a80 014 00000280: 00001a81 00001a82 00001a83 00001a84 00001a85 00001a86 00001a87 00001a88 014 00000288: 00001a89 00001a8a 00001a8b 00001a8c 00001a8d 00001a8e 00001a8f 00001a90 014 00000290: 00001a91 00001a92 00001a93 00001a94 00001a95 00001a96 00001a97 00001a98 014 00000298: 00001a99 00001a9a 00001a9b 00001a9c 00001a9d 00001a9e 00001a9f 00001aa0 015 000002a0: 00001aa1 00001aa2 00001aa3 00001aa4 00001aa5 00001aa6 00001aa7 00001aa8 015 000002a8: 00001aa9 00001aaa 00001aab 00001aac 00001aad 00001aae 00001aaf 00001ab0 015 000002b0: 00001ab1 00001ab2 00001ab3 00001ab4 00001ab5 00001ab6 00001ab7 00001ab8 015 000002b8: 00001ab9 00001aba 00001abb 00001abc 00001abd 00001abe 00001abf 00001ac0 016 000002c0: 00001ac1 00001ac2 00001ac3 00001ac4 00001ac5 00001ac6 00001ac7 00001ac8 016 000002c8: 00001ac9 00001aca 00001acb 00001acc 00001acd 00001ace 00001acf 00001ad0 016 000002d0: 00001ad1 00001ad2 00001ad3 00001ad4 00001ad5 00001ad6 00001ad7 00001ad8 016 000002d8: 00001ad9 00001ada 00001adb 00001adc 00001add 00001ade 00001adf 00001ae0 017 000002e0: 00001ae1 00001ae2 00001ae3 00001ae4 00001ae5 00001ae6 00001ae7 00001ae8 017 000002e8: 00001ae9 00001aea 00001aeb 00001aec 00001aed 00001aee 00001aef 00001af0 017 000002f0: 00001af1 00001af2 00001af3 00001af4 00001af5 00001af6 00001af7 00001af8 017 000002f8: 00001af9 00001afa 00001afb 00001afc 00001afd 00001afe 00001aff 00001b00 018 00000300: 00001b01 00001b02 00001b03 00001b04 00001b05 00001b06 00001b07 00001b08 018 00000308: 00001b09 00001b0a 00001b0b 00001b0c 00001b0d 00001b0e 00001b0f 00001b10 018 00000310: 00001b11 00001b12 00001b13 00001b14 00001b15 00001b16 00001b17 00001b18 018 00000318: 00001b19 00001b1a 00001b1b 00001b1c 00001b1d 00001b1e 00001b1f 00001b20 019 00000320: 00001b21 00001b22 00001b23 00001b24 00001b25 00001b26 00001b27 00001b28 019 00000328: 00001b29 00001b2a 00001b2b 00001b2c 00001b2d 00001b2e 00001b2f 00001b30 019 00000330: 00001b31 00001b32 00001b33 00001b34 00001b35 00001b36 00001b37 00001b38 019 00000338: 00001b39 00001b3a 00001b3b 00001b3c 00001b3d 00001b3e 00001b3f 00001b40 01a 00000340: 00001b41 00001b42 00001b43 00001b44 00001b45 00001b46 00001b47 00001b48 01a 00000348: 00001b49 00001b4a 00001b4b 00001b4c 00001b4d 00001b4e 00001b4f 00001b50 01a 00000350: 00001b51 00001b52 00001b53 00001b54 00001b55 00001b56 00001b57 00001b58 01a 00000358: 00001b59 00001b5a 00001b5b 00001b5c 00001b5d 00001b5e 00001b5f 00001b60 01b 00000360: 00001b61 00001b62 00001b63 00001b64 00001b65 00001b66 00001b67 00001b68 01b 00000368: 00001b69 00001b6a 00001b6b 00001b6c 00001b6d 00001b6e 00001b6f 00001b70 01b 00000370: 00001b71 00001b72 00001b73 00001b74 00001b75 00001b76 00001b77 00001b78 01b 00000378: 00001b79 00001b7a 00001b7b 00001b7c 00001b7d 00001b7e 00001b7f 00001b80 01c 00000380: 00001b81 00001b82 00001b83 00001b84 00001b85 00001b86 00001b87 00001b88 01c 00000388: 00001b89 00001b8a 00001b8b 00001b8c 00001b8d 00001b8e 00001b8f 00001b90 01c 00000390: 00001b91 00001b92 00001b93 00001b94 00001b95 00001b96 00001b97 00001b98 01c 00000398: 00001b99 00001b9a 00001b9b 00001b9c 00001b9d 00001b9e 00001b9f 00001ba0 01d 000003a0: 00001ba1 00001ba2 00001ba3 00001ba4 00001ba5 00001ba6 00001ba7 00001ba8 01d 000003a8: 00001ba9 00001baa 00001bab 00001bac 00001bad 00001bae 00001baf 00001bb0 01d 000003b0: 00001bb1 00001bb2 00001bb3 00001bb4 00001bb5 00001bb6 00001bb7 00001bb8 01d 000003b8: 00001bb9 00001bba 00001bbb 00001bbc 00001bbd 00001bbe 00001bbf 00001bc0 01e 000003c0: 00001bc1 00001bc2 00001bc3 00001bc4 00001bc5 00001bc6 00001bc7 00001bc8 01e 000003c8: 00001bc9 00001bca 00001bcb 00001bcc 00001bcd 00001bce 00001bcf 00001bd0 01e 000003d0: 00001bd1 00001bd2 00001bd3 00001bd4 00001bd5 00001bd6 00001bd7 00001bd8 01e 000003d8: 00001bd9 00001bda 00001bdb 00001bdc 00001bdd 00001bde 00001bdf 00001be0 01f 000003e0: 00001be1 00001be2 00001be3 00001be4 00001be5 00001be6 00001be7 00001be8 01f 000003e8: 00001be9 00001bea 00001beb 00001bec 00001bed 00001bee 00001bef 00001bf0 01f 000003f0: 00001bf1 00001bf2 00001bf3 00001bf4 00001bf5 00001bf6 00001bf7 00001bf8 01f 000003f8: 00001bf9 00001bfa 00001bfb 00001bfc 00001bfd 00001bfe 00001bff 00001c00 020 00000400: 00001c01 00001c02 00001c03 00001c04 00001c05 00001c06 00001c07 00001c08 020 00000408: 00001c09 00001c0a 00001c0b 00001c0c 00001c0d 00001c0e 00001c0f 00001c10 020 00000410: 00001c11 00001c12 00001c13 00001c14 00001c15 00001c16 00001c17 00001c18 020 00000418: 00001c19 00001c1a 00001c1b 00001c1c 00001c1d 00001c1e 00001c1f 00001c20 021 00000420: 00001c21 00001c22 00001c23 00001c24 00001c25 00001c26 00001c27 00001c28 021 00000428: 00001c29 00001c2a 00001c2b 00001c2c 00001c2d 00001c2e 00001c2f 00001c30 021 00000430: 00001c31 00001c32 00001c33 00001c34 00001c35 00001c36 00001c37 00001c38 021 00000438: 00001c39 00001c3a 00001c3b 00001c3c 00001c3d 00001c3e 00001c3f 00001c40 022 00000440: 00001c41 00001c42 00001c43 00001c44 00001c45 00001c46 00001c47 00001c48 022 00000448: 00001c49 00001c4a 00001c4b 00001c4c 00001c4d 00001c4e 00001c4f 00001c50 022 00000450: 00001c51 00001c52 00001c53 00001c54 00001c55 00001c56 00001c57 00001c58 022 00000458: 00001c59 00001c5a 00001c5b 00001c5c 00001c5d 00001c5e 00001c5f 00001c60 023 00000460: 00001c61 00001c62 00001c63 00001c64 00001c65 00001c66 00001c67 00001c68 023 00000468: 00001c69 00001c6a 00001c6b 00001c6c 00001c6d 00001c6e 00001c6f 00001c70 023 00000470: 00001c71 00001c72 00001c73 00001c74 00001c75 00001c76 00001c77 00001c78 023 00000478: 00001c79 00001c7a 00001c7b 00001c7c 00001c7d 00001c7e 00001c7f 00001c80 024 00000480: 00001c81 00001c82 00001c83 00001c84 00001c85 00001c86 00001c87 00001c88 024 00000488: 00001c89 00001c8a 00001c8b 00001c8c 00001c8d 00001c8e 00001c8f 00001c90 024 00000490: 00001c91 00001c92 00001c93 00001c94 00001c95 00001c96 00001c97 00001c98 024 00000498: 00001c99 00001c9a 00001c9b 00001c9c 00001c9d 00001c9e 00001c9f 00001ca0 025 000004a0: 00001ca1 00001ca2 00001ca3 00001ca4 00001ca5 00001ca6 00001ca7 00001ca8 025 000004a8: 00001ca9 00001caa 00001cab 00001cac 00001cad 00001cae 00001caf 00001cb0 025 000004b0: 00001cb1 00001cb2 00001cb3 00001cb4 00001cb5 00001cb6 00001cb7 00001cb8 025 000004b8: 00001cb9 00001cba 00001cbb 00001cbc 00001cbd 00001cbe 00001cbf 00001cc0 026 000004c0: 00001cc1 00001cc2 00001cc3 00001cc4 00001cc5 00001cc6 00001cc7 00001cc8 026 000004c8: 00001cc9 00001cca 00001ccb 00001ccc 00001ccd 00001cce 00001ccf 00001cd0 026 000004d0: 00001cd1 00001cd2 00001cd3 00001cd4 00001cd5 00001cd6 00001cd7 00001cd8 026 000004d8: 00001cd9 00001cda 00001cdb 00001cdc 00001cdd 00001cde 00001cdf 00001ce0 027 000004e0: 00001ce1 00001ce2 00001ce3 00001ce4 00001ce5 00001ce6 00001ce7 00001ce8 027 000004e8: 00001ce9 00001cea 00001ceb 00001cec 00001ced 00001cee 00001cef 00001cf0 027 000004f0: 00001cf1 00001cf2 00001cf3 00001cf4 00001cf5 00001cf6 00001cf7 00001cf8 027 000004f8: 00001cf9 00001cfa 00001cfb 00001cfc 00001cfd 00001cfe 00001cff 00001d00 028 00000500: 00001d01 00001d02 00001d03 00001d04 00001d05 00001d06 00001d07 00001d08 028 00000508: 00001d09 00001d0a 00001d0b 00001d0c 00001d0d 00001d0e 00001d0f 00001d10 028 00000510: 00001d11 00001d12 00001d13 00001d14 00001d15 00001d16 00001d17 00001d18 028 00000518: 00001d19 00001d1a 00001d1b 00001d1c 00001d1d 00001d1e 00001d1f 00001d20 029 00000520: 00001d21 00001d22 00001d23 00001d24 00001d25 00001d26 00001d27 00001d28 029 00000528: 00001d29 00001d2a 00001d2b 00001d2c 00001d2d 00001d2e 00001d2f 00001d30 029 00000530: 00001d31 00001d32 00001d33 00001d34 00001d35 00001d36 00001d37 00001d38 029 00000538: 00001d39 00001d3a 00001d3b 00001d3c 00001d3d 00001d3e 00001d3f 00001d40 02a 00000540: 00001d41 00001d42 00001d43 00001d44 00001d45 00001d46 00001d47 00001d48 02a 00000548: 00001d49 00001d4a 00001d4b 00001d4c 00001d4d 00001d4e 00001d4f 00001d50 02a 00000550: 00001d51 00001d52 00001d53 00001d54 00001d55 00001d56 00001d57 00001d58 02a 00000558: 00001d59 00001d5a 00001d5b 00001d5c 00001d5d 00001d5e 00001d5f 00001d60 02b 00000560: 00001d61 00001d62 00001d63 00001d64 00001d65 00001d66 00001d67 00001d68 02b 00000568: 00001d69 00001d6a 00001d6b 00001d6c 00001d6d 00001d6e 00001d6f 00001d70 02b 00000570: 00001d71 00001d72 00001d73 00001d74 00001d75 00001d76 00001d77 00001d78 02b 00000578: 00001d79 00001d7a 00001d7b 00001d7c 00001d7d 00001d7e 00001d7f 00001d80 02c 00000580: 00001d81 00001d82 00001d83 00001d84 00001d85 00001d86 00001d87 00001d88 02c 00000588: 00001d89 00001d8a 00001d8b 00001d8c 00001d8d 00001d8e 00001d8f 00001d90 02c 00000590: 00001d91 00001d92 00001d93 00001d94 00001d95 00001d96 00001d97 00001d98 02c 00000598: 00001d99 00001d9a 00001d9b 00001d9c 00001d9d 00001d9e 00001d9f 00001da0 02d 000005a0: 00001da1 00001da2 00001da3 00001da4 00001da5 00001da6 00001da7 00001da8 02d 000005a8: 00001da9 00001daa 00001dab 00001dac 00001dad 00001dae 00001daf 00001db0 02d 000005b0: 00001db1 00001db2 00001db3 00001db4 00001db5 00001db6 00001db7 00001db8 02d 000005b8: 00001db9 00001dba 00001dbb 00001dbc 00001dbd 00001dbe 00001dbf 00001dc0 02e 000005c0: 00001dc1 00001dc2 00001dc3 00001dc4 00001dc5 00001dc6 00001dc7 00001dc8 02e 000005c8: 00001dc9 00001dca 00001dcb 00001dcc 00001dcd 00001dce 00001dcf 00001dd0 02e 000005d0: 00001dd1 00001dd2 00001dd3 00001dd4 00001dd5 00001dd6 00001dd7 00001dd8 02e 000005d8: 00001dd9 00001dda 00001ddb 00001ddc 00001ddd 00001dde 00001ddf 00001de0 02f 000005e0: 00001de1 00001de2 00001de3 00001de4 00001de5 00001de6 00001de7 00001de8 02f 000005e8: 00001de9 00001dea 00001deb 00001dec 00001ded 00001dee 00001def 00001df0 02f 000005f0: 00001df1 00001df2 00001df3 00001df4 00001df5 00001df6 00001df7 00001df8 02f 000005f8: 00001df9 00001dfa 00001dfb 00001dfc 00001dfd 00001dfe 00001dff 00001e00 030 00000600: 00001e01 00001e02 00001e03 00001e04 00001e05 00001e06 00001e07 00001e08 030 00000608: 00001e09 00001e0a 00001e0b 00001e0c 00001e0d 00001e0e 00001e0f 00001e10 030 00000610: 00001e11 00001e12 00001e13 00001e14 00001e15 00001e16 00001e17 00001e18 030 00000618: 00001e19 00001e1a 00001e1b 00001e1c 00001e1d 00001e1e 00001e1f 00001e20 031 00000620: 00001e21 00001e22 00001e23 00001e24 00001e25 00001e26 00001e27 00001e28 031 00000628: 00001e29 00001e2a 00001e2b 00001e2c 00001e2d 00001e2e 00001e2f 00001e30 031 00000630: 00001e31 00001e32 00001e33 00001e34 00001e35 00001e36 00001e37 00001e38 031 00000638: 00001e39 00001e3a 00001e3b 00001e3c 00001e3d 00001e3e 00001e3f 00001e40 032 00000640: 00001e41 00001e42 00001e43 00001e44 00001e45 00001e46 00001e47 00001e48 032 00000648: 00001e49 00001e4a 00001e4b 00001e4c 00001e4d 00001e4e 00001e4f 00001e50 032 00000650: 00001e51 00001e52 00001e53 00001e54 00001e55 00001e56 00001e57 00001e58 032 00000658: 00001e59 00001e5a 00001e5b 00001e5c 00001e5d 00001e5e 00001e5f 00001e60 033 00000660: 00001e61 00001e62 00001e63 00001e64 00001e65 00001e66 00001e67 00001e68 033 00000668: 00001e69 00001e6a 00001e6b 00001e6c 00001e6d 00001e6e 00001e6f 00001e70 033 00000670: 00001e71 00001e72 00001e73 00001e74 00001e75 00001e76 00001e77 00001e78 033 00000678: 00001e79 00001e7a 00001e7b 00001e7c 00001e7d 00001e7e 00001e7f 00001e80 034 00000680: 00001e81 00001e82 00001e83 00001e84 00001e85 00001e86 00001e87 00001e88 034 00000688: 00001e89 00001e8a 00001e8b 00001e8c 00001e8d 00001e8e 00001e8f 00001e90 034 00000690: 00001e91 00001e92 00001e93 00001e94 00001e95 00001e96 00001e97 00001e98 034 00000698: 00001e99 00001e9a 00001e9b 00001e9c 00001e9d 00001e9e 00001e9f 00001ea0 035 000006a0: 00001ea1 00001ea2 00001ea3 00001ea4 00001ea5 00001ea6 00001ea7 00001ea8 035 000006a8: 00001ea9 00001eaa 00001eab 00001eac 00001ead 00001eae 00001eaf 00001eb0 035 000006b0: 00001eb1 00001eb2 00001eb3 00001eb4 00001eb5 00001eb6 00001eb7 00001eb8 035 000006b8: 00001eb9 00001eba 00001ebb 00001ebc 00001ebd 00001ebe 00001ebf 00001ec0 036 000006c0: 00001ec1 00001ec2 00001ec3 00001ec4 00001ec5 00001ec6 00001ec7 00001ec8 036 000006c8: 00001ec9 00001eca 00001ecb 00001ecc 00001ecd 00001ece 00001ecf 00001ed0 036 000006d0: 00001ed1 00001ed2 00001ed3 00001ed4 00001ed5 00001ed6 00001ed7 00001ed8 036 000006d8: 00001ed9 00001eda 00001edb 00001edc 00001edd 00001ede 00001edf 00001ee0 037 000006e0: 00001ee1 00001ee2 00001ee3 00001ee4 00001ee5 00001ee6 00001ee7 00001ee8 037 000006e8: 00001ee9 00001eea 00001eeb 00001eec 00001eed 00001eee 00001eef 00001ef0 037 000006f0: 00001ef1 00001ef2 00001ef3 00001ef4 00001ef5 00001ef6 00001ef7 00001ef8 037 000006f8: 00001ef9 00001efa 00001efb 00001efc 00001efd 00001efe 00001eff 00001f00 038 00000700: 00001f01 00001f02 00001f03 00001f04 00001f05 00001f06 00001f07 00001f08 038 00000708: 00001f09 00001f0a 00001f0b 00001f0c 00001f0d 00001f0e 00001f0f 00001f10 038 00000710: 00001f11 00001f12 00001f13 00001f14 00001f15 00001f16 00001f17 00001f18 038 00000718: 00001f19 00001f1a 00001f1b 00001f1c 00001f1d 00001f1e 00001f1f 00001f20 039 00000720: 00001f21 00001f22 00001f23 00001f24 00001f25 00001f26 00001f27 00001f28 039 00000728: 00001f29 00001f2a 00001f2b 00001f2c 00001f2d 00001f2e 00001f2f 00001f30 039 00000730: 00001f31 00001f32 00001f33 00001f34 00001f35 00001f36 00001f37 00001f38 039 00000738: 00001f39 00001f3a 00001f3b 00001f3c 00001f3d 00001f3e 00001f3f 00001f40 03a 00000740: 00001f41 00001f42 00001f43 00001f44 00001f45 00001f46 00001f47 00001f48 03a 00000748: 00001f49 00001f4a 00001f4b 00001f4c 00001f4d 00001f4e 00001f4f 00001f50 03a 00000750: 00001f51 00001f52 00001f53 00001f54 00001f55 00001f56 00001f57 00001f58 03a 00000758: 00001f59 00001f5a 00001f5b 00001f5c 00001f5d 00001f5e 00001f5f 00001f60 03b 00000760: 00001f61 00001f62 00001f63 00001f64 00001f65 00001f66 00001f67 00001f68 03b 00000768: 00001f69 00001f6a 00001f6b 00001f6c 00001f6d 00001f6e 00001f6f 00001f70 03b 00000770: 00001f71 00001f72 00001f73 00001f74 00001f75 00001f76 00001f77 00001f78 03b 00000778: 00001f79 00001f7a 00001f7b 00001f7c 00001f7d 00001f7e 00001f7f 00001f80 03c 00000780: 00001f81 00001f82 00001f83 00001f84 00001f85 00001f86 00001f87 00001f88 03c 00000788: 00001f89 00001f8a 00001f8b 00001f8c 00001f8d 00001f8e 00001f8f 00001f90 03c 00000790: 00001f91 00001f92 00001f93 00001f94 00001f95 00001f96 00001f97 00001f98 03c 00000798: 00001f99 00001f9a 00001f9b 00001f9c 00001f9d 00001f9e 00001f9f 00001fa0 03d 000007a0: 00001fa1 00001fa2 00001fa3 00001fa4 00001fa5 00001fa6 00001fa7 00001fa8 03d 000007a8: 00001fa9 00001faa 00001fab 00001fac 00001fad 00001fae 00001faf 00001fb0 03d 000007b0: 00001fb1 00001fb2 00001fb3 00001fb4 00001fb5 00001fb6 00001fb7 00001fb8 03d 000007b8: 00001fb9 00001fba 00001fbb 00001fbc 00001fbd 00001fbe 00001fbf 00001fc0 03e 000007c0: 00001fc1 00001fc2 00001fc3 00001fc4 00001fc5 00001fc6 00001fc7 00001fc8 03e 000007c8: 00001fc9 00001fca 00001fcb 00001fcc 00001fcd 00001fce 00001fcf 00001fd0 03e 000007d0: 00001fd1 00001fd2 00001fd3 00001fd4 00001fd5 00001fd6 00001fd7 00001fd8 03e 000007d8: 00001fd9 00001fda 00001fdb 00001fdc 00001fdd 00001fde 00001fdf 00001fe0 03f 000007e0: 00001fe1 00001fe2 00001fe3 00001fe4 00001fe5 00001fe6 00001fe7 00001fe8 03f 000007e8: 00001fe9 00001fea 00001feb 00001fec 00001fed 00001fee 00001fef 00001ff0 03f 000007f0: 00001ff1 00001ff2 00001ff3 00001ff4 00001ff5 00001ff6 00001ff7 00001ff8 03f 000007f8: 00001ff9 00001ffa 00001ffb 00001ffc 00001ffd 00001ffe 00001fff 00002000Schematic here:
zip
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Comments
ptr long 0 count long 0 ' copy line size from shifted line size get_values mov ptr, hubaddr ' get hub address 'copy hub address to ptr, don't trash hub address mov count, line_size ' get line_size 'copy line size to count shr count, #1 ' shift data to word alligned from byte ' shr vmaddr, #1 ' shift data to word alligned from byte 'prepare for command mov dirb,latchvalue ' make copy of latchvalue here for restore or outa,maskP16P20 ' set control pins high or dira,maskP16P20 ' set control pins P16-P20 as outputs get_values_ret retThen do transfer.
Errors are: Not real sure what I'm looking at. Any help would be greatly appreciated!
First thing I need to know, using the cache driver, does it always live in it's own cog? Or is it dynamically loaded? I'm hoping it's the former because it should make adding extended functions much easier.
Now a note to myself... It works, passes all tests
{ Skeleton JCACHE external RAM driver Copyright (c) 2011 by David Betz Based on code by Steve Denson (jazzed) Copyright (c) 2010 by John Steven Denson Inspired by VMCOG - virtual memory server for the Propeller Copyright (c) February 3, 2010 by William Henning TERMS OF USE: MIT License Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. } CON ' default cache dimensions DEFAULT_INDEX_WIDTH = 6 DEFAULT_OFFSET_WIDTH = 7 ' cache line tag flags EMPTY_BIT = 30 DIRTY_BIT = 31 PUB image return @init_vm DAT org $0 ' initialization structure offsets ' $0: pointer to a two word mailbox ' $4: pointer to where to store the cache lines in hub ram ' $8: number of bits in the cache line index if non-zero (default is DEFAULT_INDEX_WIDTH) ' $a: number of bits in the cache line offset if non-zero (default is DEFAULT_OFFSET_WIDTH) ' note that $4 must be at least 2^(index_width+offset_width) bytes in size ' the cache line mask is returned in $0 init_vm mov t1, par ' get the address of the initialization structure rdlong pvmcmd, t1 ' pvmcmd is a pointer to the virtual address and read/write bit mov pvmaddr, pvmcmd ' pvmaddr is a pointer into the cache line on return add pvmaddr, #4 add t1, #4 rdlong cacheptr, t1 ' cacheptr is the base address in hub ram of the cache add t1, #4 rdlong t2, t1 wz if_nz mov index_width, t2 ' override the index_width default value add t1, #4 rdlong t2, t1 wz if_nz mov offset_width, t2 ' override the offset_width default value mov index_count, #1 shl index_count, index_width mov index_mask, index_count sub index_mask, #1 mov line_size, #1 shl line_size, offset_width mov t1, line_size sub t1, #1 wrlong t1, par ' put external memory initialization here shr line_size, #1 ' divide lenght by two for word-byte after response - jsd ' shr line_size, #1 ' divide lenght by two for word-byte after response - jsd ' mov frqa, _frqa ' setup NCO freq ' mov frqb, _frqb ' setup EDGE freq 'init 'set up latches here or outa,maskP22 ' pin 22 high or dira,maskP22 ' and now set as an output 'mov dirb, #%11111111 'set latch All hi ' Initialise hardware tristates everything and read/write set the pins 'done mov err, #0 ' reset err=false=good mov latchvalue, #%11111111 ' resset latch value call #set373 'and set latch and dira,maskP0P20low ' tristates all the common pins, leaves P22 as is though jmp #vmflush fillme long 0[128-fillme] ' first 128 cog locations are used for a direct mapped cache table fit 128 ' initialize the cache lines vmflush movd :flush, #0 mov t1, index_count :flush mov 0-0, empty_mask add :flush, dstinc djnz t1, #:flush ' start the command loop waitcmd wrlong zero, pvmcmd :wait rdlong vmline, pvmcmd wz if_z jmp #:wait shr vmline, offset_width wc ' carry is now one for read and zero for write mov set_dirty_bit, #0 ' make mask to set dirty bit on writes muxnc set_dirty_bit, dirty_mask mov line, vmline ' get the cache line index and line, index_mask mov hubaddr, line shl hubaddr, offset_width add hubaddr, cacheptr ' get the address of the cache line wrlong hubaddr, pvmaddr ' return the address of the cache line movs :ld, line movd :st, line :ld mov vmcurrent, 0-0 ' get the cache line tag and vmcurrent, tag_mask cmp vmcurrent, vmline wz ' z set means there was a cache hit if_nz call #miss ' handle a cache miss :st or 0-0, set_dirty_bit ' set the dirty bit on writes jmp #waitcmd ' wait for a new command ' line is the cache line index ' vmcurrent is current cache line ' vmline is new cache line ' hubaddr is the address of the cache line miss movd :test, line movd :st, line :test test 0-0, dirty_mask wz if_z jmp #:rd ' current cache line is clean, just read new one mov vmaddr, vmcurrent shl vmaddr, offset_width call #wr_cache_line ' write current cache line :rd mov vmaddr, vmline shl vmaddr, offset_width call #rd_cache_line ' read new cache line :st mov 0-0, vmline miss_ret ret ' pointers to mailbox entries pvmcmd long 0 ' on call this is the virtual address and read/write bit pvmaddr long 0 ' on return this is the address of the cache line containing the virtual address cacheptr long 0 ' address in hub ram where cache lines are stored vmline long 0 ' cache line containing the virtual address vmcurrent long 0 ' current selected cache line (same as vmline on a cache hit) line long 0 ' current cache line index set_dirty_bit long 0 ' DIRTY_BIT set on writes, clear on reads zero long 0 ' zero constant dstinc long 1<<9 ' increment for the destination field of an instruction t1 long 0 ' temporary variable t2 long 0 ' temporary variable tag_mask long !(1<<DIRTY_BIT) ' includes EMPTY_BIT index_width long DEFAULT_INDEX_WIDTH index_mask long 0 index_count long 0 offset_width long DEFAULT_OFFSET_WIDTH line_size long 0 ' line size in bytes empty_mask long (1<<EMPTY_BIT) dirty_mask long (1<<DIRTY_BIT) ' input parameters to rd_cache_line and wr_cache_line vmaddr long 0 ' external address hubaddr long 0 ' hub memory address ptr long 0 count long 0 ' copy line size from shifted line size ' Initialise hardware tristates everything and read/write set the pins ' and dira,maskP0P20low ' tristates all the common pins, leaves P22 as is though ' ----------------- common routines ------------------------------------- 'get_values rdlong hubaddr, hubptr ' get hub address ' rdlong ramaddr, ramptr ' get ram address ' rdlong len, lenptr ' get length ' mov err, #5 ' err=5 ' or outa,maskP16P20 ' set control pins high ' or dira,maskP16P20 ' set control pins P16-P20 as outputs 'get_values_ret ret get_values mov ptr, hubaddr ' get hub address mov count, line_size ' get ram address 'shr count, #1 ' shift data to word alligned from byte 'shr vmaddr, #1 ' shift data to word alligned from byte mov dirb,latchvalue ' make copy of latchvalue here for restore or outa,maskP16P20 ' set control pins high or dira,maskP16P20 ' set control pins P16-P20 as outputs get_values_ret ret set373 or outa,maskP22 ' pin 22 high or dira,#%1_11111111 ' enable pins 0-7 and 8 as outputs and outa,maskP0P8low ' P0-P8 low or outa,latchvalue ' send out the data or outa,maskP8 ' P8 high, clocks out data andn outa,maskP22 ' pin 22 low set373_ret ret set161 mov latchvalue,#%11111110 ' group 1, displays all off call #set373 ' send out to the latch and outa,maskP0P20low '%11111111_11100000_00000000_00000000 or dira,maskP0P20 '%00000000_00011111_11111111_11111111 or outa,vmaddr ' send out ramaddr or outa,maskP20 ' clock high or outa,maskP19 ' load high or outa,maskP16P20 ' set control pins high mov latchvalue,#%11111101 ' group 2, displays all off call #set373 ' send out to the latch set161_ret ret 'stop jmp #stop ' for debugging 'delaynop nop ' nop ' nop ' nop 'delaynop_ret ret '---------------------------------------------------------------------------------------------------- ' ' wr_cache_line - write a cache line to external memory ' ' vmaddr is the external memory address to write ' hubaddr is the hub memory address to read ' line_size is the number of bytes to write ' '---------------------------------------------------------------------------------------------------- wr_cache_line ' command S pasmhubtoram call #get_values ' get hubaddr,ramaddr,len and set control pins call #set161 hubtoram_loop and outa,maskP16P31 '%11111111_11111111_00000000_00000000 ' clear for output rdword data_16,ptr ' get the word from hub and data_16,maskP0P15 ' mask to a word only or outa,data_16 ' send out the byte to P0-P15 andn outa,maskP17 ' set mem write low add ptr,#2 ' increment by 2 bytes = 1 word. Put this here for small delay while writes or outa,maskP17 ' mem write high andn outa,maskP20 ' clock 161 low or outa,maskP20 ' clock 161 high djnz count,#hubtoram_loop ' loop this many times mov latchvalue, dirb ' restore latch value call #set373 and dira, maskP0P20low ' tristates all the common pins, leaves P22 as is though ' jmp #done ' tristate pins and listen for commands ' command S wr_cache_line_ret ret '---------------------------------------------------------------------------------------------------- ' ' rd_cache_line - read a cache line from external memory ' ' vmaddr is the external memory address to read ' hubaddr is the hub memory address to write ' line_size is the number of bytes to read ' '---------------------------------------------------------------------------------------------------- rd_cache_line ' command T pasmramtohub call #get_values ' get hubaddr,ramaddr,len and set control pins call #set161 and dira,maskP16P31 '%11111111_11111111_00000000_00000000 inputs andn outa,maskP16 ' memory /rd low ramtohub_loop mov data_16,ina ' get the data wrword data_16,ptr ' move data to hub andn outa,maskP20 ' clock 161 low or outa,maskP20 ' clock 161 high add ptr,#2 ' increment the hub address djnz count,#ramtohub_loop or outa,maskP16 ' memory /rd high mov latchvalue, dirb ' restore latch value call #set373 and dira,maskP0P20low ' tristates all the common pins, leaves P22 as is though ' rd_cache_line_ret ret ' variables pasm_n long 0 ' general purpose value data_16 long 0 ' general purpose value latchvalue long %00000000_00000000_00000000_00000000 ' current 373 value ' constants 'Zero long %00000000_00000000_00000000_00000000 ' used in several places maskP0P2low long %11111111_11111111_11111111_11111000 ' P0-P2 low maskP0P20 long %00000000_00011111_11111111_11111111 ' P0-P18 enabled for output plus P19,P20 maskP0P18low long %11111111_11111000_00000000_00000000 ' P0-P18 low maskP16 long %00000000_00000001_00000000_00000000 ' pin 16 maskP17 long %00000000_00000010_00000000_00000000 ' pin 17 maskP18 long %00000000_00000100_00000000_00000000 ' pin 18 maskP19 long %00000000_00001000_00000000_00000000 ' pin 19 maskP20 long %00000000_00010000_00000000_00000000 ' pin 20 maskP22 long %00000000_01000000_00000000_00000000 ' pin 22 maskP16P31 long %11111111_11111111_00000000_00000000 ' pin 16 to pin 31 maskP0P15 long %00000000_00000000_11111111_11111111 ' for masking words maskP16P20 long %00000000_00011111_00000000_00000000 maskP0P20low long %11111111_11100000_00000000_00000000 ' for returning all group pins HiZ maskP16P17P20 long %00000000_00010011_00000000_00000000 maskP0P8low long %11111111_11111111_11111110_00000000 ' P0-P7 low maskP8 long %00000000_00000000_00000001_00000000 ' pin 8 { get_values mov ptr, hubaddr ' get hub address mov count, line_size ' get ram address ' shr count, #1 ' shift data to word alligned from byte shr vmaddr, #1 ' shift data to word alligned from byte mov dirb,latchvalue ' make copy of latchvalue here for restore or outa,maskP16P20 ' set control pins high or dira,maskP16P20 ' set control pins P16-P20 as outputs get_values_ret ret set373 or outa,maskP22 ' pin 22 high or dira,#%1_11111111 ' enable pins 0-7 and 8 as outputs and outa,maskP0P8low ' P0-P8 low or outa,latchvalue ' send out the data or outa,maskP8 ' P8 high, clocks out data andn outa,maskP22 ' pin 22 low set373_ret ret set161 mov latchvalue,#%11111110 ' group 1, displays all off call #set373 ' send out to the latch and outa,maskP0P20low '%11111111_11100000_00000000_00000000 or dira,maskP0P20 '%00000000_00011111_11111111_11111111 or outa,vmaddr ' send out ramaddr or outa,maskP20 ' clock high or outa,maskP19 ' load high or outa,maskP16P20 ' set control pins high set161_ret ret done mov latchvalue, dirb ' restore latch value call #set373 and dira,maskP0P20low ' tristates all the common pins, leaves P22 as is though done_ret ret fit 496The next experiment is to get burst reads working. Then a drystone!
{ Skeleton JCACHE external RAM driver Copyright (c) 2011 by David Betz Based on code by Steve Denson (jazzed) Copyright (c) 2010 by John Steven Denson Inspired by VMCOG - virtual memory server for the Propeller Copyright (c) February 3, 2010 by William Henning For the TouchBurger By James Moxham and Joe Heinz Basic port by Joe Heinz, Optimizations by Steve Denson Copyright (c) 2012 by John Steven Denson and Joe Heinz TERMS OF USE: MIT License Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. } CON ' default cache dimensions DEFAULT_INDEX_WIDTH = 6 DEFAULT_OFFSET_WIDTH = 7 ' cache line tag flags EMPTY_BIT = 30 DIRTY_BIT = 31 PUB image return @init_vm DAT org $0 ' initialization structure offsets ' $0: pointer to a two word mailbox ' $4: pointer to where to store the cache lines in hub ram ' $8: number of bits in the cache line index if non-zero (default is DEFAULT_INDEX_WIDTH) ' $a: number of bits in the cache line offset if non-zero (default is DEFAULT_OFFSET_WIDTH) ' note that $4 must be at least 2^(index_width+offset_width) bytes in size ' the cache line mask is returned in $0 init_vm mov t1, par ' get the address of the initialization structure rdlong pvmcmd, t1 ' pvmcmd is a pointer to the virtual address and read/write bit mov pvmaddr, pvmcmd ' pvmaddr is a pointer into the cache line on return add pvmaddr, #4 add t1, #4 rdlong cacheptr, t1 ' cacheptr is the base address in hub ram of the cache add t1, #4 rdlong t2, t1 wz if_nz mov index_width, t2 ' override the index_width default value add t1, #4 rdlong t2, t1 wz if_nz mov offset_width, t2 ' override the offset_width default value mov index_count, #1 shl index_count, index_width mov index_mask, index_count sub index_mask, #1 mov line_size, #1 shl line_size, offset_width mov t1, line_size sub t1, #1 wrlong t1, par ' put external memory initialization here or outa,maskP22 ' pin 22 high or dira,maskP22 ' and now set P22 as an output mov dirb, #%11111111 ' set latch All hi ' Initialise hardware tristates everything and read/write set the pins call #release shr line_size, #1 ' divide lenght by two for word-byte after response - jsd jmp #vmflush fillme long 0[128-fillme] ' first 128 cog locations are used for a direct mapped cache table fit 128 ' initialize the cache lines vmflush movd :flush, #0 mov t1, index_count :flush mov 0-0, empty_mask add :flush, dstinc djnz t1, #:flush ' start the command loop waitcmd wrlong zero, pvmcmd :wait rdlong vmline, pvmcmd wz if_z jmp #:wait shr vmline, offset_width wc ' carry is now one for read and zero for write mov set_dirty_bit, #0 ' make mask to set dirty bit on writes muxnc set_dirty_bit, dirty_mask mov line, vmline ' get the cache line index and line, index_mask mov hubaddr, line shl hubaddr, offset_width add hubaddr, cacheptr ' get the address of the cache line wrlong hubaddr, pvmaddr ' return the address of the cache line movs :ld, line movd :st, line :ld mov vmcurrent, 0-0 ' get the cache line tag and vmcurrent, tag_mask cmp vmcurrent, vmline wz ' z set means there was a cache hit if_nz call #miss ' handle a cache miss :st or 0-0, set_dirty_bit ' set the dirty bit on writes jmp #waitcmd ' wait for a new command ' line is the cache line index ' vmcurrent is current cache line ' vmline is new cache line ' hubaddr is the address of the cache line miss movd :test, line movd :st, line :test test 0-0, dirty_mask wz if_z jmp #:rd ' current cache line is clean, just read new one mov vmaddr, vmcurrent shl vmaddr, offset_width call #wr_cache_line ' write current cache line :rd mov vmaddr, vmline shl vmaddr, offset_width call #rd_cache_line ' read new cache line :st mov 0-0, vmline miss_ret ret ' pointers to mailbox entries pvmcmd long 0 ' on call this is the virtual address and read/write bit pvmaddr long 0 ' on return this is the address of the cache line containing the virtual address cacheptr long 0 ' address in hub ram where cache lines are stored vmline long 0 ' cache line containing the virtual address vmcurrent long 0 ' current selected cache line (same as vmline on a cache hit) line long 0 ' current cache line index set_dirty_bit long 0 ' DIRTY_BIT set on writes, clear on reads zero long 0 ' zero constant dstinc long 1<<9 ' increment for the destination field of an instruction t1 long 0 ' temporary variable t2 long 0 ' temporary variable tag_mask long !(1<<DIRTY_BIT) ' includes EMPTY_BIT index_width long DEFAULT_INDEX_WIDTH index_mask long 0 index_count long 0 offset_width long DEFAULT_OFFSET_WIDTH line_size long 0 ' line size in bytes empty_mask long (1<<EMPTY_BIT) dirty_mask long (1<<DIRTY_BIT) ' input parameters to rd_cache_line and wr_cache_line vmaddr long 0 ' external address hubaddr long 0 ' hub memory address ptr long 0 len long 0 get_values mov dirb,latchvalue ' make copy of latchvalue here for restore ''All changes to latch value applied to dirb or outa,maskP16P20 ' set control pins high or dira,maskP16P20 ' set control pins P16-P20 as outputs mov len, line_size ' make a copy of line_size AND. mov ptr, hubaddr ' hubaddr = hub page address shr vmaddr, #1 ' schematic connects SRAM A0 to A0, not A1 - jsd andn vmaddr, maskP0P18low get_values_ret ret set373 or outa,maskP22 ' pin 22 high or dira,#%1_11111111 ' enable pins 0-7 and 8 as outputs and outa,maskP0P8low ' P0-P8 low ''P8 is made low at the same time as P0-P7 or outa,latchvalue ' send out the data or outa,maskP8 ' P8 high, clocks out data andn outa,maskP22 ' pin 22 low set373_ret ret set161 mov latchvalue,#%11111110 ' group 1, displays all off call #set373 ' send out to the latch and outa,maskP0P20low '%11111111_11100000_00000000_00000000 or dira,maskP0P20 '%00000000_00011111_11111111_11111111 or outa,vmaddr ' send out ramaddr or outa,maskP20 ' P20 clock high or outa,maskP19 ' p19 load high andn outa,maskP20 ' clock low andn outa,maskP19 ' load low or outa,maskP16P20 ' P16-P20 high in case the next thing is a group change and P16/P17 are low and hence upset the ram chip set161_ret ret set161and373 call #set161 ' pass ramaddr mov latchvalue,#%11111101 ' group 2 call #set373 ' change to group 2 set161and373_ret ret release mov latchvalue, dirb ' restore latch value call #set373 ' and update latch and dira,maskP0P20low ' tristates all the common pins, leaves P22 as is though release_ret ret '---------------------------------------------------------------------------------------------------- ' ' wr_cache_line - write a cache line to external memory ' ' vmaddr is the external memory address to write ' hubaddr is the hub memory address to read ' line_size is the number of bytes to write ' '---------------------------------------------------------------------------------------------------- wr_cache_line pasmhubtoram call #get_values sub vmaddr,#1 '?????? call #set161and373 ' set up the 161 counter and then change to group 2 'or dira,maskP0P15 ' %00000000_00000000_11111111_11111111 ' data bus outputs ''Pins set as output by Set161 'ctr setup for burst read mov phsa, wr_phsa ' init counters phsa mov frqa, wr_frqa ' setup NCO freq andn outa,maskP20 ' start counters rdword data_16,ptr ' sync up only mov ctra, _ctra ' enable address counter clk ' 5MB/s write loop uses ctra for address clock hubtoram_loop and outa,maskP16P31 '%11111111_11111111_00000000_00000000 clear for output rdword data_16,ptr ' get the word from hub or outa,data_16 ' send out the byte to P0-P15 andn outa,maskP17 ' set mem write low add ptr,#2 ' increment by 2 bytes = 1 word. Put this here for small delay while writes or outa,maskP17 ' mem write high djnz len,#hubtoram_loop ' loop this many times or outa,maskP20 ' stop clock ' mov ctra, #0 ' stop counter call #release wr_cache_line_ret ret '---------------------------------------------------------------------------------------------------- ' ' rd_cache_line - read a cache line from external memory ' ' vmaddr is the external memory address to read ' hubaddr is the hub memory address to write ' line_size is the number of bytes to read ' '---------------------------------------------------------------------------------------------------- rd_cache_line pasmramtohub call #get_values call #set161and373 ' set up the 161 counter and change to group 2 and dira,maskP16P31 '%11111111_11111111_00000000_00000000 inputs andn outa,maskP16 ' memory /rd low 'ctr setup for burst read mov phsa, #0 ' init counters phsa mov frqa, rd_frqa ' setup NCO freq mov phsb, ptr ' save hub ptr to phsb mov frqb, #2 ' setup EDGE freq andn outa,maskP20 ' start counters mov ctrb, rd_ctrb ' set ctr be mode rdword data_16,phsb ' sync up only mov ctra, _ctra ' enable address counter clk ' 10MB/s read loop uses phsb for hub pointer ramtohub_loop mov data_16,ina ' get first data wrword data_16,phsb ' move data to hub djnz len,#ramtohub_loop or outa,maskP20 ' stop clock mov ctra, #0 ' stop counter mov ctrb, #0 ' stop counter or outa,maskP16 ' memory /rd high call #release rd_cache_line_ret ret ' variables data_32 long 0 pasm_n long 0 ' general purpose value data_16 long 0 ' general purpose value latchvalue long %00000000_00000000_00000000_00000000 ' current 373 value ' constants maskP0P2low long %11111111_11111111_11111111_11111000 ' P0-P2 low maskP0P20 long %00000000_00011111_11111111_11111111 ' P0-P18 enabled for output plus P19,P20 maskP0P18low long %11111111_11111000_00000000_00000000 ' P0-P18 low maskP16 long %00000000_00000001_00000000_00000000 ' pin 16 maskP17 long %00000000_00000010_00000000_00000000 ' pin 17 maskP18 long %00000000_00000100_00000000_00000000 ' pin 18 maskP19 long %00000000_00001000_00000000_00000000 ' pin 19 maskP20 long %00000000_00010000_00000000_00000000 ' pin 20 maskP22 long %00000000_01000000_00000000_00000000 ' pin 22 maskP16P31 long %11111111_11111111_00000000_00000000 ' pin 16 to pin 31 maskP0P15 long %00000000_00000000_11111111_11111111 ' for masking words maskP16P20 long %00000000_00011111_00000000_00000000 maskP0P20low long %11111111_11100000_00000000_00000000 ' for returning all group pins HiZ maskP16P17P20 long %00000000_00010011_00000000_00000000 maskP0P8low long %11111111_11111111_11111110_00000000 ' P0-P7 low maskP8 long %00000000_00000000_00000001_00000000 ' pin 8 '-------------------------------------------------------------------------- ' setups needed for burst read/write Thanks to Jazzed (Steve Denson) '-------------------------------------------------------------------------- _ctra long 4<<26 | 20 ' NCO mode on P20 ds_frq long $2000_0000 ' 10 MHZ ds_ctrb long 4<<26 | 18 ' NCO mode on P18 rd_frqa long $1000_0000 ' 5 MHZ rd_ctrb long $A<<26| 20 ' Edge Accumulate mode on P20 wr_phsa long $8800_0000 ' phsa offset for adjusting clock start wr_frqa long $0800_0000 ' 2.5 MHZ fit 496XMMC
Dhrystone Benchmark, Version C, Version 2.2 Program compiled without 'register' attribute Using STDC clock(), HZ=80000000 Trying 5000 runs through Dhrystone: Final values of the variables used in the benchmark: Int_Glob: 5 should be: 5 Bool_Glob: 1 should be: 1 Ch_1_Glob: A should be: A Ch_2_Glob: B should be: B Arr_1_Glob[8]: 7 should be: 7 Arr_2_Glob[8][7]: 5010 should be: Number_Of_Runs + 10 Ptr_Glob-> Ptr_Comp: 14056 should be: (implementation-dependent) Discr: 0 should be: 0 Enum_Comp: 2 should be: 2 Int_Comp: 17 should be: 17 Str_Comp: DHRYSTONE PROGRAM, SOME STRING should be: DHRYSTONE PROGRAM, SOME STRING Next_Ptr_Glob-> Ptr_Comp: 14056 should be: (implementation-dependent), same as above Discr: 0 should be: 0 Enum_Comp: 1 should be: 1 Int_Comp: 18 should be: 18 Str_Comp: DHRYSTONE PROGRAM, SOME STRING should be: DHRYSTONE PROGRAM, SOME STRING Int_1_Loc: 5 should be: 5 Int_2_Loc: 13 should be: 13 Int_3_Loc: 7 should be: 7 Enum_Loc: 1 should be: 1 Str_1_Loc: DHRYSTONE PROGRAM, 1'ST STRING should be: DHRYSTONE PROGRAM, 1'ST STRING Str_2_Loc: DHRYSTONE PROGRAM, 2'ND STRING should be: DHRYSTONE PROGRAM, 2'ND STRING Microseconds for one run through Dhrystone: 735 Dhrystones per Second: 1358XMM-single
Dhrystone Benchmark, Version C, Version 2.2 Program compiled without 'register' attribute Using STDC clock(), HZ=80000000 Trying 5000 runs through Dhrystone: Final values of the variables used in the benchmark: Int_Glob: 5 should be: 5 Bool_Glob: 1 should be: 1 Ch_1_Glob: A should be: A Ch_2_Glob: B should be: B Arr_1_Glob[8]: 7 should be: 7 Arr_2_Glob[8][7]: 5010 should be: Number_Of_Runs + 10 Ptr_Glob-> Ptr_Comp: 536899232 should be: (implementation-dependent) Discr: 0 should be: 0 Enum_Comp: 2 should be: 2 Int_Comp: 17 should be: 17 Str_Comp: DHRYSTONE PROGRAM, SOME STRING should be: DHRYSTONE PROGRAM, SOME STRING Next_Ptr_Glob-> Ptr_Comp: 536899232 should be: (implementation-dependent), same as above Discr: 0 should be: 0 Enum_Comp: 1 should be: 1 Int_Comp: 18 should be: 18 Str_Comp: DHRYSTONE PROGRAM, SOME STRING should be: DHRYSTONE PROGRAM, SOME STRING Int_1_Loc: 5 should be: 5 Int_2_Loc: 13 should be: 13 Int_3_Loc: 7 should be: 7 Enum_Loc: 1 should be: 1 Str_1_Loc: DHRYSTONE PROGRAM, 1'ST STRING should be: DHRYSTONE PROGRAM, 1'ST STRING Str_2_Loc: DHRYSTONE PROGRAM, 2'ND STRING should be: DHRYSTONE PROGRAM, 2'ND STRING Microseconds for one run through Dhrystone: 1306 Dhrystones per Second: 765Now I need to figure out how to stuff our transfers into the cache driver. It should be possible to use the extended commands to invoke HUB2ram, Hub2display, Ram2hub and Ram2Display. From my understanding, I can call the cog commands but all the current spin code needs to be translated to C+?