prop vsu pll mode 1, 500khz lower limit of pll mode questions.

IncVoid

So I was reading the hydra manual and the prop manual, they both are saying the vsu is clocked not by the master clock, but by the pll of the cog counter. That will only go as low as 500khz, 4mhz using 1/8th tap.

I was hoping to hook up the pin group of my choice to leds instead of the resister network on the hydra that creates the voltages for the ntsc signal.
Clock the vsu ultra slow so I could "see" the signal being sent out on the 3 pins. Seeing the vsu do its modulation.
I'm a poor man, have no scope so I can't see a signal.

Any way to manually clock the vsu? How far down can you clock the pll modes before damage occurs.
I was assuming that inside the chip has set values for the resisters and caps and whatever is needed to get the pll working, which is why its always 4-8mhz regardless of master clock frequency.
anybody chime in and tell me "thats just the way it is"

Phil Pilgrim (PhiPi)

That's mostly just the way it is. It's a physical limit: the PLL simply cannot lock on an input frequency much below 4 MHz. That said, however, you may be able to increase the vscl register values enough to slow the video output. Unfortunately, this would have to be done in multiple places in the driver and it may still not slow things down to the point that you can see the changes happen.

-Phil

IncVoid

I completely forgot about that! the per pixel time can be varied.

Thanks for the response! I'll give it a good thought.