Single-transistor (1T) SRAM cells - Could it be used on Prop II ?

Cluso99

Here is a company that licenses a 1T SRAM cell, amongst other things.
http://www.eejournal.com/archives/articles/20120613-mosys/

I am not sure if the prop uses a 4T or 6T SRAM cell. So 4x or 6x 128KB would be a huge improvement, presuming of course the license fees were reasonable and the 1T cell would work on the geometry the P2 will be using.

jmg

1T SRAMs are DRAMs, so they need a refresh handler -
Of course, with the round-robin nature of COG access, this could be managed at the (low) cost of another time slot(s).
Standard DRAM tend to not manage random access so well, but a small cache system would help there.

If it really did need to be slower, I'm sure users could live with a faster DATA segment of SRAM, and a larger slightly slower DRAM area.

The nice low-voltage/low frequency operation of Static SRAM would be lost, but I guess Prop II is not really a micro-power sandpit player.

Cluso99

Here is what the article says...

MoSys created the single-transistor (1T) SRAM cell, which you could license for inclusion in your own chip. 1T SRAMs are a lot smaller than traditional six-transistor SRAM cells, so the MoSys technology was good for packing a lot of memory into a little space.

So, I presume they do in fact mean SRAM not DRAM. I think it's worth investigating.

Phil Pilgrim (PhiPi)

Any memory cell with just one transistor is gonna be current-guzzling hog. 'Remember NMOS microprocessors?

-Phil

jmg

Cluso99 wrote: »

So, I presume they do in fact mean SRAM not DRAM. I think it's worth investigating.

Here are some details
http://en.wikipedia.org/wiki/1T-SRAM

Hidden refresh and pseudostatic are the important qualifiers...
( There is no such thing as a free lunch...)

- but still, well worth including into something like a Prop II - especially as the Main memory is a little MHz-decoupled from the real engines in the COGs.