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Propeller 2 mul asm command question — Parallax Forums

Propeller 2 mul asm command question

ElectrodudeElectrodude Posts: 1,665
edited 2012-06-01 08:38 in Propeller 1
Why is the Prop 2's mul assembly command only 24 bits? 32 bits would make much more sense because it's a 32 bit processor. Is there not enough space for ~500 more transistors per cog or did I miss something?

The link to the specifications pdf is: http://www.parallaxsemiconductor.com/sites/default/files/parallax/Propeller2DetailedPreliminaryFeatureList-v2.0.pdf. The mul command is explained on p7.

Thanks,
Electrodude

Comments

  • pedwardpedward Posts: 1,642
    edited 2012-05-31 16:40
    Chip probably felt a 24bit single cycle instruction was sufficient, that's why he also created the 32bit multi-cycle state machine.

    Chip is nearly never arbitrary, he probably decided it was a ridiculous amount more to do single cycle 32x32 mul and settled at 23x23 mul. For may operations, I'm certain people who NEED single cycle mul will learn to live with 24bits or figure out another way of multiplying their numbers, perhaps with the CORDIC instructions.
  • Cluso99Cluso99 Posts: 18,069
    edited 2012-05-31 17:55
    Electrodude wrote: »
    Why is the Prop 2's mul assembly command only 24 bits? 32 bits would make much more sense because it's a 32 bit processor. Is there not enough space for ~500 more transistors per cog or did I miss something?

    The link to the specifications pdf is: http://www.parallaxsemiconductor.com/sites/default/files/parallax/Propeller2DetailedPreliminaryFeatureList-v2.0.pdf. The mul command is explained on p7.

    Thanks,
    Electrodude
    500 transistors x8 probably will not fit in the limited space in the centre of the die. That space is fixed, and there are already compromises, particularly hub space. Everything is a trade-off. Of course, if Chip went to 25m we could have 100's of cogs and MB's of hub ram (think what you could do with 4B transistors)
  • Heater.Heater. Posts: 21,230
    edited 2012-05-31 18:43
    I don't have much idea how multiplier circuits look but I get the impression that for a single cycle mul the number of transistors required goes up with the square of the number of bits. So limiting to 24 bits might be saving a lot whilst still being useful in the majority of practical cases.
    Where does the number 500 come from? Sounds a bit low to me.
  • Dave HeinDave Hein Posts: 6,347
    edited 2012-05-31 18:50
    The hardware multiplier was orignally described as a 16-bit multiplier. So, 24 bits is an improvement over the original design. A 24-bit multiplier is useful for single-precision floating point, which is probably why it was increased from 16 bits.
  • Heater.Heater. Posts: 21,230
    edited 2012-05-31 19:09
    24 bit mul for floating point. Of course. Brilliant!
  • Roy ElthamRoy Eltham Posts: 3,000
    edited 2012-05-31 21:55
    Just to clarify (as some people have sort of mentioned) there is a "full 32x32 into 64bit result" multiply available, it's just multiple cycles and the result goes in a special register.
  • ElectrodudeElectrodude Posts: 1,665
    edited 2012-06-01 08:38
    I saw the floating point thing somewhere but forgot about it. 24x24 will make masking unnecessary for floats. I saw the scaling thing for the accumulator but couldn't really understand how it worked (just a shift?). Now that I do the math, 32*32*16 transistors per adder bit*8 cogs=131072 transistors for 32x32, while 24*24*16 transistors per adder bit*8 cogs=73728 transistors for 24x24. That's 57344 more and almost twice as many transistors. I don't know what the current transistor limit is, but that seems like a lot more.

    Thanks,
    electrodude
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