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UPEW & Prop II: Have the videos of Chip & Beau's talk been posted? If so, where? — Parallax Forums

UPEW & Prop II: Have the videos of Chip & Beau's talk been posted? If so, where?

Cluso99Cluso99 Posts: 18,069
edited 2012-04-29 16:43 in Propeller 1
The title says it all.
Unfortunately I was tied up when Chip's talk was on (thanks tubular for the text alerting me that it was on).

Looking forward to hear what was presented on the P2. Anyone have any details they could post?

Postedit: Here is a link (thanks tubular) - the video links are at the bottom of this linked page. Chips talk is the second on and about 6? hours in.
http://forums.parallax.com/content.php?62-Parallax-Expo-was-a-Huge-Success

Comments

  • pedwardpedward Posts: 1,642
    edited 2012-04-15 17:19
    2 months they should send off for a shuttle run, they expect 25-40 chips back from that. Chip has to start work on the ROM code before the shuttle run. Beau added an M6 layer to the top to distribute power to the chip. Chip revealed they were going to add a little logic to tri-state the outputs so you can multiplex the DACs. Each pin has a 75 ohm 9 bit DAC -- this is dithered to 18bit resolution. 126K of RAM, 180Mhz clock speed in worst case conditions. Will use a 20Mhz external crystal in Chip's example -- the clock control is integer instead of binary, so a multiplier of 9 * 20Mhz gets 180Mhz.
  • jmgjmg Posts: 15,183
    edited 2012-04-15 18:11
    No YouTube links to presentations yet ?
    pedward wrote: »
    Each pin has a 75 ohm 9 bit DAC -- this is dithered to 18bit resolution. 126K of RAM, 180Mhz clock speed in worst case conditions....

    Those DACs are very impressive, but I just want the Prop II to do the simple things well : Like external capture and edge-generate, to SysCLK resolutions...
  • RaymanRayman Posts: 14,833
    edited 2012-04-16 17:17
    I don't think there was too much new info since last Expo... They do seem very close this time.
    New version of Spin will include structures. Maybe that will apply to Prop1, not sure.
    I think Chip said the price will only be ~20% more than Prop1.
    SDRAM is the main target for external memory. Chip likes the 32MB you can get for $3.
    We'll be able to show an HD image using SDRAM as a frame buffer.

    I think 256 color mode is going to be the way to go since each cog has a 256 long CLUT.
    Wish we had it now, it'd make my next project a lot simpler and lower cost...
  • pedwardpedward Posts: 1,642
    edited 2012-04-16 18:36
    Rayman wrote: »
    I don't think there was too much new info since last Expo... They do seem very close this time.
    New version of Spin will include structures. Maybe that will apply to Prop1, not sure.
    I think Chip said the price will only be ~20% more than Prop1.
    SDRAM is the main target for external memory. Chip likes the 32MB you can get for $3.
    We'll be able to show an HD image using SDRAM as a frame buffer.

    I think 256 color mode is going to be the way to go since each cog has a 256 long CLUT.
    Wish we had it now, it'd make my next project a lot simpler and lower cost...

    Yeah, couple of details, Chip is doing 1080p at 30Hz right now (I think), but 1080i or 720p will be necessary to have *ANY* bandwidth to write to the external RAM.

    The Prop2 now implements basically what VGA did, a Palette DAC that you program 256 of your favorite colors into, then it uses those for the DAC output. The big difference is that the Prop 2 implements RGBA instead of 6:6:6 like VGA.

    You can do all sorts of funky stuff with palette rotation, animation, without the bit pushing.
  • Invent-O-DocInvent-O-Doc Posts: 768
    edited 2012-04-17 21:42
    The palette rotation will be so much fun like programming an eight bit atari.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-04-17 21:52
    Rayman wrote:
    SDRAM is the main target for external memory. Chip likes the 32MB you can get for $3.
    SDRAM is such a volatile product, though. Who knows if something compatible with the Prop II will even be available several years hence.

    -Phil
  • TubularTubular Posts: 4,706
    edited 2012-04-17 22:32
    In case you missed it, links to the recordings are posted at the bottom of this thread
    http://forums.parallax.com/content.php?62-Parallax-Expo-was-a-Huge-Success!
  • pedwardpedward Posts: 1,642
    edited 2012-04-17 23:31
    Phil Pilgrim (PhiPi) wrote: »
    SDRAM is such a volatile product, though. Who knows if something compatible with the Prop II will even be available several years hence.

    -Phil

    The interface Chip designed isn't specific to SDRAM, just like the "video" circuit isn't actually a video circuit. He designed it to do 16 or 32bit bulk transfers to/from the CLUT, the COG has to do all the setup and housekeeping for the SDRAM, the Prop 2 doesn't implement any of that. It's the genericness of the design that will make it so powerful (like pushing bits out to an LCD display or some such).
  • jmgjmg Posts: 15,183
    edited 2012-04-17 23:51
    pedward wrote: »
    He designed it to do 16 or 32bit bulk transfers to/from the CLUT, the COG has to do all the setup and housekeeping for the SDRAM, the Prop 2 doesn't implement any of that.

    So does the hardware handle the DDR clocking, and Data transfer, or is that still a SW-bash task ?

    What about RAS and CAS - is that under "setup and housekeeping", or under "bulk transfers to/from the CLUT" ?

    What speeds can SDRAM operate at, and what COG bandwidth is consumed doing this ?
  • pedwardpedward Posts: 1,642
    edited 2012-04-18 00:44
    The bulk transfers will handle clocking and data transfer, but the COG has to do the RAS/CAS setup first. Chip alluded to SDRAMs not being fast enough to clock at full speed, however I'm sure there has to be a 180Mhz SDRAM out there somewhere. It doesn't do DDR AFAIK.

    Each COG has a dedicated state machine for doing bulk transfers, so the COG can be doing something else while the data is being read to/from the CLUT. Chip intended for the COG to be performing RDQUADC or WRQUAD in conjunction with the external memory; a dedicated COG would become a memory server that swapped pages in/out of Hub memory. When doing video display, you setup the bulk transfer to dump data into the CLUT while you are rendering pixels. At that point the CLUT is dynamic, but the pixel data is very monotonic, since it references the CLUT in a loop -- push pixel 0...push pixel 255, load CLUT, push pixel 0...push pixel 255...

    Also to note, COG RAM is 4 way ported, there are 3 read ports and 1 read/write port. This is how he can do a quad read, I believe it also allude to the 4 cycle approach. 3 of the 4 cycles are read (instruction, src, dst) and 1 cycle is write (result written to destination). This also explains the 4 stage pipelining.

    I hope there will be more formal documentation about the microarchitecture, since the Prop 2 will be more difficult to program for, but potentially has a lot more exploitable features. Because a lot of the features were developed incrementally, they rely on separate state machines, achieving a good level of parallelism. The bulk transfer to/from the CLUT and the chip-to-chip comms are good examples of operations that happen in the background.

    The chip-to-chip comms has double buffering in the state machine, so you can receive 1 long while the previously received long is waiting for the COG to service it. The COG can then do blocking or non-blocking reads by setting a flag (I'm unclear exactly which). When a "wc" is specified [I think] the COG doesn't block and the carry flag indicates whether there was data transferred during the instruction. If you don't "wc" then the COG blocks until data is available.

    Those state machines, combined with the caching and QUAD instructions, offer a much higher I/O and memory bandwidth capability.

    Also, the DACs are 500Mhz max bandwidth, but only get used up to ~230Mhz in Video processing IIRC. The I/O comparators are limited to 30Mhz, I don't know if the ADCs have the same limitation, but I think they will.
  • tonyp12tonyp12 Posts: 1,951
    edited 2012-04-27 09:18
    "Chip alluded to SDRAMs not being fast enough to clock at full speed, however I'm sure there has to be a 180Mhz"

    Here is a 200mhz one: (store 2'097'152 longs)
    http://www.micron.com/parts/dram/sdram/mt48lc2m32b2p-5?pc={428A5CC9-2A78-447E-939B-6F3A40D538C6}
    or similar from Issi:
    http://www.issi.com/pdf/42-45S32200L.pdf

    So no DDR support?
    Maybe with some trickery you could read every even longs and with inverted clock-phase to read odds, it's like having two additional master banks.

    Could you use a so-dimm?, eight times the storage of above for same $5 price.(64bit bus though, could you select hi/low longs for a 32bit bus ?)
    http://www.ebay.com/itm/64MB-MEMORY-8X64-PC133-7NS-3-3V-SDRAM-144-PIN-SO-DIMM-/140627893664?pt=LH_DefaultDomain_0&hash=item20be135da0
    They even got a 100pack for $2 each of the 64MB sticks
  • evanhevanh Posts: 16,112
    edited 2012-04-27 20:31
    pedward wrote: »
    Yeah, couple of details, Chip is doing 1080p at 30Hz right now (I think), but 1080i or 720p will be necessary to have *ANY* bandwidth to write to the external RAM.

    Small detail: 1080p30 is actually 1080i60 in terms of data rate and signalling, ie: screenmode. Monitors/TVs generally don't handle less than 50Hz.

    That's the little secret of progressive in general I think. It's actually interlaced signalling but the second half is from the same frame as the first half. Result is, so called progressive doesn't really exist as a separate screenmode as it's just a half framerate interlace.

    VGA like screenmodes are called sequential.
  • evanhevanh Posts: 16,112
    edited 2012-04-27 20:48
    tonyp12 wrote: »
    Could you use a so-dimm?, eight times the storage of above for same $5 price.(64bit bus though, could you select hi/low longs for a 32bit bus ?)

    One option is use half the DIMM and forget the rest.
  • vanmunchvanmunch Posts: 568
    edited 2012-04-28 19:22
    Here is the link to the video I took of there of Chip & Beau's talk:
    http://youtu.be/5d_T0BK3ttg

    My wife and I wrote an article about the expo that's going to be in the next issue of ROBOT. The article will have a link to ~11 videos that I took of talks, demos (flam bot, paintball..), and the tour. Enjoy!
  • tonyp12tonyp12 Posts: 1,951
    edited 2012-04-29 16:01
    Chip says that groups of 8 pins will have their own Vdd and Vss.

    For a simple direct audio 2V rms drive, can Vss be a negative voltage?
    And the built-in DAC will produce (I guess +1.5v to -1.5v?) signal that don't need large blocking caps?
  • jmgjmg Posts: 15,183
    edited 2012-04-29 16:25
    tonyp12 wrote: »
    Chip says that groups of 8 pins will have their own Vdd and Vss.

    For a simple direct audio 2V rms drive, can Vss be a negative voltage?
    And the built-in DAC will produce +1.5v to -1.5v signal that don't need large blocking caps?

    Some nice wishful thinking there, but sorry, no.
    Vss is usually common across the die, and multiple Vdd allow 1.8V / 2.5V / 3.3v domains

    Someone is listening tho, I see Nuvoton have an Audio DAC, without blocking caps, and they do that with an on-chip charge pump

    http://www.nuvoton.com/NuvotonMOSS/Community/ProductInfo.aspx?tp_GUID=8c8ce332-3114-4bad-b581-7bfca589c913
  • tonyp12tonyp12 Posts: 1,951
    edited 2012-04-29 16:43
    Bummer.
    If the built-in 75ohm dac can not do negative rail., might as well use the video circuit to feed a I2S signal to one of these:
    http://www.mouser.com/Semiconductors/Audio-ICs/Audio-D-A-Converter-ICs/_/N-4gxkeZscv7?Keyword=rms
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