Need circuit to output pulses only if a second input is high at the rising edge...

Bean

Okay, I'm drawing a blank about how to do this.
I need a circuit (not code) that will pass a clock pulse ONLY if a second input is high at the rising edge of the clock pulse.

Here is what I mean:

The INPUT B pulse get output'ed ONLY if INPUT A is high at the rising edge of INPUT B

           ____      ____        ____      ____    ____
INPUT A  _|    |____|    |______|    |____|    |__|    |__

            ____      ____      ____      ____      ____
INPUT B  __|    |____|    |____|    |____|    |____|    |__

            ____      ____                          ____
OUTPUT   __|    |____|    |________________________|    |__

Any ideas... I sure some kind of flip-flop can do it...

Bean

Beau Schwabe

Use a JK flip flop with a clear.... a 7473 would work... in fact a 7473 has two JK flip flops, if you used both of them, you'd have two output pulses. One would only pulse in input A lagged input B and the other would only pulse if input B lagged input A.

Bean

Thanks Beau,
It's been a long time since I played around with flip-flops, can you tell me how I would connect that ?

Thanks,
Bean

Beau Schwabe

I might have the lead/lag backwards, but this should do the trick.

erco

@Beau: Now THAT would be a great line follower course.

Beau Schwabe

@Erco - lol

@Bean - If you need to preserve the lagging pulse width, which by your diagram, it looks like you might adding an OR and an AND gate will work. The first part of the circuit just determines which pulse comes first and produces a 'composite' difference of the two incoming pulses. by adding the simple OR/AND latch on the composite output you can hold the pulse until the laging pulse finishes instead of the leading pulse finishing.

Bean

Beau,
I'll try that.
The two clocks will be almost the same frequency, so depending on the phase the pulse would be very short without stretching it.

Bean