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Prop1 - Inter-cog communication via Port B? — Parallax Forums

Prop1 - Inter-cog communication via Port B?

ctwardellctwardell Posts: 1,716
edited 2012-03-11 00:39 in Propeller 1
I seem to recall some threads discussing if this was possible, but can't find them.

So the question is, can cogs communicate via Port B?

If say Cog1 writes a value to OUTB, can Cog2 see that value by reading INB, assuming DIRB has all pins set as outputs.

Thanks,

C.W.

Comments

  • Cluso99Cluso99 Posts: 18,069
    edited 2012-03-09 07:17
    The port b is not implemented. i.e. there are no wires internally :(
  • Duane DegnDuane Degn Posts: 10,588
    edited 2012-03-09 07:19
    I remember these discussions. I'm pretty sure just about positive, Port B isn't internally connected to anything. I think you can use INB and OUTB for scratch pad RAM but not for inter-cog communication.
  • Cluso99Cluso99 Posts: 18,069
    edited 2012-03-09 17:17
    Duane, etc. I am certain. There is no PortB hardware. I wanted to use it a long time ago and specifically asked Chip. That is why we now have PortD in P2 because of these requests.
  • ctwardellctwardell Posts: 1,716
    edited 2012-03-09 18:00
    Bummer...

    Thanks for the replies.

    I'll have to make due with shared hub locations until Prop 2 arrives.

    C.W.
  • Cluso99Cluso99 Posts: 18,069
    edited 2012-03-10 13:49
    If you have any spare pins, you can use that. But I guess you are like the rest of us... no pins!
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-03-10 16:02
    Almost everyone has one spare pin: SCL. Once the program has loaded from EEPROM, and if you don't need further access to it, you can use SCL for inter-cog signalling. As long as SDA is tri-stated and remains pulled high, you won't be causing any interaction with the EEPROM, since no START conditions occur.

    -Phil
  • Cluso99Cluso99 Posts: 18,069
    edited 2012-03-11 00:31
    Phil Pilgrim (PhiPi) wrote: »
    Almost everyone has one spare pin: SCL. Once the program has loaded from EEPROM, and if you don't need further access to it, you can use SCL for inter-cog signalling. As long as SDA is tri-stated and remains pulled high, you won't be causing any interaction with the EEPROM, since no START conditions occur.

    -Phil
    Nope: I use both SCL and SDA for other things like /R & /W to SRAM. Then 1 for /CE & CS combined and inverted, 8 for data, 19 for address. Leaves 2 pins and I have to talk to something external on them ;)
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-03-11 00:39
    Why separate pins for /R and /W? They're mutually exclusive, and both are typically gated on the memory chip by the enable pins. So do the same as you did for /CE and CS with an external inverter.

    -Phil
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