I see that those fractions add up to .8431372583393682, but how did you come up with those particular values?
I cheated a little, and used Wolfram..
The reason Egyptian fraction work nicely, is it is the same as a variable modulus counter, in this example /7 or /8
If you divide by 7 exactly half of the time, and by 8 exactly half, you will average divide by 7.5,
so the Egyptian fraction tells you what ratio of the time to divide by which whole number, to fit.
The size of the fractions, tells you how often a period difference will be seen.
In this example, the actual frequency is not really 10.2M, it is
80e6/(2^32/(round(2^32/(80e6/10.20e6)))) = 10199999.995529651 Hz, and
if we do
ef=1/2 + 1/3 + 1/102 + 1/290917621
(ef = Egyptian Fraction)
and apply that fraction to the TIME DOMAIN, as the ratio of two possible periods summed, we get an average value of
1/((7/80e6)*(1-ef)+(8/80e6)*ef) = 10199999.99552966233
These agree to ~ 1 part in 10^15.
The general form is always ef*PeriodDivisionChoiceA + (1-ef)*PeriodDivisionChoiceB
I'll add: This maths also nicely reminds the user they do not actually get
10199999.995529651 Hz, even though 80e6/(2^32/(round(2^32/(80e6/10.20e6)))) suggests they do.
What you actually get (& can see above on the scope plots) is two frequencies,
1/((7/80e6)) = 11428571.42857142Hz
1/((8/80e6)) = 10000000Hz
and the average calculated, is really the long term average of these two choices.
Where you said "This permits limited duty cycle adjustment, so long as each half period is no longer than about 133 system clocks.
"
I think you meant to say "so long as each half period is no shorter than about 133 system clocks" ?
Another common switching driver topology is a Bridge, where every alternate pulse swaps between two pins. The ON times are common between the pins, to keep magnetic balance, and ideally should adjust to 0 (or close) for soft start
Each pin cannot (should not) go above 50% duty.
- with this control you can tune resonance, via frequency, and also tune circulating energy (via ON times)
Where you said "This permits limited duty cycle adjustment, so long as each half period is no longer than about 133 system clocks." I think you meant to say "so long as each half period is no shorter than about 133 system clocks" ?
The object works great. Two counters per cog each running in NCO differential mode (to provide the signal for a MOSFET gate driver which in turn switches two MOSFETs in a high frequency half-bridge resonator).
The object more effectively utilizes the Propeller for this project: 14 counters with two pins per counter equals 28 pins total.
There are many of these circuits that will be used to replace a single high power supply.
Thanks for your help guys... I'll keep you posted on the outcome.
sm
P.S. I assume that the phase adjust value ($8000_0000 + 6) includes additional clock cycles to make up for the subtraction and negation instructions but why six instead of 8?
test inp,maska wz 'Has pina changed?
if_z jmp #testb ' No: Try pinb.
rdlong perioda,par ' Yes: Read latest periods for ctra.
test prev,maska wz ' Was previous input a zero?
if_z shr perioda,#16 ' Yes: Use high 16 bits of period.
and perioda,_0xffff ' Mask off period for other half cycle.
sub perioda,phaseadj ' Subtract the phase adjust constant.
sub perioda,phsa ' Subtract the current phase.
neg phsa,perioda ' Write adjusted phase to phsa.
prev long 0 'Previous pin states. Always starts out as low:low
_0xffff long $ffff 'Period mask.
phaseadj long $8000_0000 + 6 'Phase adjustment added to phsa is $8000_0000 - period.
acc res 1 'Scratch register.
inp res 1 'Input anded with pin mask and XORed with previous input.
maska res 1 'Mask for pina.
maskb res 1 'Mask for pinb.
addrb res 1 'Address of phaseb long in hub.
perioda res 1 'Half period of ctra.
periodb res 1 'Half period of ctrb.
Why six instead of eight? Actually, the question is, "Why six instead of four?" The reason is that the source read of phsa in the sub operation occurs in a different part of the four-stage pipeline than the destination write in the neg statement. BTW, I didn't try to figure it out a priori. I just adjusted it until the frequency was right. Sometimes the empirical approach is quicker than actually knowing what you're doing.
Fourteen well-tempered frequencies and and still one cog and lots of hub left to implement exactly the flexible application-specific tuning interface you need! It's an elegant solution, the sort of thing the Prop was made for, I think. If you find you need a fast serial port or something like that in order to implement the interface, well, you still have 12 frequencies.
The caveat that "so long as each half period is no shorter than about 133 system clocks" is a rather big fish hook.
It is nice to be able to drop duty cycles to close to zero, for soft start / short circuit hiccup conditions.
I think I can get it down to ~28 cycles for a preferred pulse ( ie min _/=\_ ) , and ~36 for the non-preferred (ie =\_/= )
Next challenge is to add Alternate-drive for bridge applications, but that will cost cycles, and I'm unsure what the Prop does as CTR is dynamically flipped across pins ?
It would usually be when both are low, so I guess a pin defined as L, will stay low ?
I have not seen Gate Drivers with a FlipFlip built in, as the PWM controllers usually have that.
I guess an external 1G74 would save pins ?
Out of curiousity... You used the word "pulse" in the title... Can you have a fixed pulse frequency but with a pulse width that varies?
(like a faster version of servo control). If so, maybe there's some trick you could do...
Anyway, if you need several of these outputs, isn't it better to use one cog to do them all in assembly anyway?
If that is done with the cog counters, the main steps come between division of phsa into 400 steps for close to 200 kHz, and division into 399 steps for 200,501 Hz, or 401 steps for 199501 Hz.
The ones with odd numbers of steps are asymmetric, that is, one half cycle is 12.5ns shorter than the other. So, the symmetrical main step with the cog counters is also about 1kHz like Phil pointed out.
The counters can achieve intermediate values, but that is accomplished with bobble, jitter, whatever you want to call it. For example, 200250 Hz is comprised of alternating cycles of the periods corresponding to about 200000 Hz and 200501 Hz. That goes back to the talk about exotic fractions.
Here is an update to the original object which adds NCO differential mode and a PST user interface(using 6 cogs per Tracy Allen suggestion so that control can be added). My programming technique is kind of stone club and axe but I think it works OK. I also rearranged the pin assignments (all ctra pins assigned and then all ctrb pins assigned)
Comments
I will test it out as soon as I can get back to my lab on Monday.
Some people are blessed with both brains and compassion... thanks Phil.
sm
I cheated a little, and used Wolfram..
The reason Egyptian fraction work nicely, is it is the same as a variable modulus counter, in this example /7 or /8
If you divide by 7 exactly half of the time, and by 8 exactly half, you will average divide by 7.5,
so the Egyptian fraction tells you what ratio of the time to divide by which whole number, to fit.
The size of the fractions, tells you how often a period difference will be seen.
In this example, the actual frequency is not really 10.2M, it is
80e6/(2^32/(round(2^32/(80e6/10.20e6)))) = 10199999.995529651 Hz, and
if we do
ef=1/2 + 1/3 + 1/102 + 1/290917621
(ef = Egyptian Fraction)
and apply that fraction to the TIME DOMAIN, as the ratio of two possible periods summed, we get an average value of
1/((7/80e6)*(1-ef)+(8/80e6)*ef) = 10199999.99552966233
These agree to ~ 1 part in 10^15.
The general form is always ef*PeriodDivisionChoiceA + (1-ef)*PeriodDivisionChoiceB
I'll add: This maths also nicely reminds the user they do not actually get
10199999.995529651 Hz, even though 80e6/(2^32/(round(2^32/(80e6/10.20e6)))) suggests they do.
What you actually get (& can see above on the scope plots) is two frequencies,
1/((7/80e6)) = 11428571.42857142Hz
1/((8/80e6)) = 10000000Hz
and the average calculated, is really the long term average of these two choices.
Attached is the jitter-free clocks program in a more usable object form.
-Phil
"
I think you meant to say "so long as each half period is no shorter than about 133 system clocks" ?
Another common switching driver topology is a Bridge, where every alternate pulse swaps between two pins. The ON times are common between the pins, to keep magnetic balance, and ideally should adjust to 0 (or close) for soft start
Each pin cannot (should not) go above 50% duty.
- with this control you can tune resonance, via frequency, and also tune circulating energy (via ON times)
-Phil
The object more effectively utilizes the Propeller for this project: 14 counters with two pins per counter equals 28 pins total.
There are many of these circuits that will be used to replace a single high power supply.
Thanks for your help guys... I'll keep you posted on the outcome.
sm
P.S. I assume that the phase adjust value ($8000_0000 + 6) includes additional clock cycles to make up for the subtraction and negation instructions but why six instead of 8?
test inp,maska wz 'Has pina changed? if_z jmp #testb ' No: Try pinb. rdlong perioda,par ' Yes: Read latest periods for ctra. test prev,maska wz ' Was previous input a zero? if_z shr perioda,#16 ' Yes: Use high 16 bits of period. and perioda,_0xffff ' Mask off period for other half cycle. sub perioda,phaseadj ' Subtract the phase adjust constant. sub perioda,phsa ' Subtract the current phase. neg phsa,perioda ' Write adjusted phase to phsa. prev long 0 'Previous pin states. Always starts out as low:low _0xffff long $ffff 'Period mask. phaseadj long $8000_0000 + 6 'Phase adjustment added to phsa is $8000_0000 - period. acc res 1 'Scratch register. inp res 1 'Input anded with pin mask and XORed with previous input. maska res 1 'Mask for pina. maskb res 1 'Mask for pinb. addrb res 1 'Address of phaseb long in hub. perioda res 1 'Half period of ctra. periodb res 1 'Half period of ctrb.'Glad it worked out for you!
Why six instead of eight? Actually, the question is, "Why six instead of four?" The reason is that the source read of phsa in the sub operation occurs in a different part of the four-stage pipeline than the destination write in the neg statement. BTW, I didn't try to figure it out a priori. I just adjusted it until the frequency was right. Sometimes the empirical approach is quicker than actually knowing what you're doing.
-Phil
It is nice to be able to drop duty cycles to close to zero, for soft start / short circuit hiccup conditions.
I think I can get it down to ~28 cycles for a preferred pulse ( ie min _/=\_ ) , and ~36 for the non-preferred (ie =\_/= )
Next challenge is to add Alternate-drive for bridge applications, but that will cost cycles, and I'm unsure what the Prop does as CTR is dynamically flipped across pins ?
It would usually be when both are low, so I guess a pin defined as L, will stay low ?
I have not seen Gate Drivers with a FlipFlip built in, as the PWM controllers usually have that.
I guess an external 1G74 would save pins ?
For anyone interested I ran it in the Propeller emulator - Gear (screen capture below)
(like a faster version of servo control). If so, maybe there's some trick you could do...
Anyway, if you need several of these outputs, isn't it better to use one cog to do them all in assembly anyway?
-Phil
http://obex.parallax.com/objects/359/
-Phil
The ones with odd numbers of steps are asymmetric, that is, one half cycle is 12.5ns shorter than the other. So, the symmetrical main step with the cog counters is also about 1kHz like Phil pointed out.
The counters can achieve intermediate values, but that is accomplished with bobble, jitter, whatever you want to call it. For example, 200250 Hz is comprised of alternating cycles of the periods corresponding to about 200000 Hz and 200501 Hz. That goes back to the talk about exotic fractions.
SM