P8x32B

Circuitsoft

What would it cost to develop/release a Prop 1 with Port B available, in a QFP-80? No change to core, clocking, or ram. I wonder if, at this point, the remaining development effort on the Prop II might be serial enough to squeeze Prop1B development in parallel.

Paul Baker wrote: »

It has been completed, but the LVS utility chokes on the design. Until we can resolve this issue, the P8X32B (Prop-1 w/ 64 I/O) will remain on the shelf.

Has this been resolved?

Why? P8x32A is a much lower-power processor than the Prop II, but can still benefit from more I/Os.

pedward

I queried Chip about this a little, I get the sense that if he were to pursue that project again, he'd do it differently. When he started the P2, he went about it using the same process as the P1, designing everything in schematic form, then doing layout. He said a good part of the development timeline has been restarting from scratch using Verilog.

I would bet that if Chip pursued the B rev, he'd rewrite the Prop 1 in Verilog and do a fresh layout. You could bet that he wouldn't leave the Prop 1B alone and most likely it would have hardware MUL, just like the book says.

The Prop 2 isn't 100% binary compatible (AFAIK) with the Prop 1, but the Prop 1B could easily replace the Prop 1A and be 100% code compatible.

For the 32 pin I/O packages, it just wouldn't have the Port B brought out to pins. This would permit Port B to be used like Port D is used in the Prop 2.

I wouldn't expect a Prop 1B anytime soon after the Prop 2, they would need to recover the dev costs of the Prop 2 and justify the development and mask for the Prop 1B.

Circuitsoft

Would the Prop1B, designed with that methodology, have the same or better power consumption as the Prop1A? Would it clock higher?

pedward

My bet is that it would clock higher because the design is much simpler than the p2. Based on his work on the p2, I would guess at least twice the clock speed. I have no idea about the power, but I would bet he would do it in 180nm to get economies of scale, since he could use the same fab as the p2. Just my speculation.

Toby Seckshund

In the past this question usually gets the "Don't try to distract Chip" or "The shuttle runs would cost $100K+" replies.

When I win the lottery ...

Circuitsoft

I doubt it would be 180nm, as it's been stated that the Prop II would have much higher static current draw due to the smaller process, and low static draw is one of the advantages of the prop I over the prop II.

evanh

Umm, I'd think it'd stay at the lower density to keep the very low power consumption and also the 3.3v core voltage. It want's to be a drop-in replacement. Presumably this would in-turn keep the maximum clockrate similar to the existing Prop1.