My Propeller II vs Propeller III
ori
Posts: 1
Hi everyone,
Propeller chip is awesome but I would like to share my point of view on how Propeller II should be.
Propeller I is awesome, easy to use even by non professional users but with some small improvements would be perfect for all. Without changing a lot of things (like planned with Propeller II) it should be enough keeping the same core with some some small additions
1) 64 KByte Hub RAM
2) Fast InterCOG communication registers
3) 64 Kb of onchip EEPROM (and free 2 more i/o pin).
I know that true Propeller II is coming (for me this is propeller III !!!) but while mantaing full backward compatibility I think that listed additions will greatly improve the yet great propeller!
Regards
Massimo
Propeller chip is awesome but I would like to share my point of view on how Propeller II should be.
Propeller I is awesome, easy to use even by non professional users but with some small improvements would be perfect for all. Without changing a lot of things (like planned with Propeller II) it should be enough keeping the same core with some some small additions
1) 64 KByte Hub RAM
actually with 32 KB, too many cogs and not enough memory to run them.
Trick: 60K RAM and last 4K bootloader in rom ($F002 to $FFFF)
Trick: 60K RAM and last 4K bootloader in rom ($F002 to $FFFF)
2) Fast InterCOG communication registers
now you cannot directly communicate data between cogs without wasting time passing through HUB RAM. Hub RAM access i too slow if you want to exploit high speed parallesim with more COGS. I think that a bounch of "multiport" registers accessible at the same time from multiple cogs will greatly improve speeds in many situations. Please note that even only one of such registers will be useful, more are welcome, of course.
Trick: What about mapping this register like PORTB ?
Trick: What about mapping this register like PORTB ?
3) 64 Kb of onchip EEPROM (and free 2 more i/o pin).
64 KB for RAM image
I know that true Propeller II is coming (for me this is propeller III !!!) but while mantaing full backward compatibility I think that listed additions will greatly improve the yet great propeller!
Regards
Massimo
Comments
About really fast intercog-communication you could use IO-pins.
If I remember right the propeller-die has RAMadresses for DIRB OUTB INB
but I'm not sure if the belong to hub-RAM with its 7-22 cycle accesstime or not
best regards
Stefan
Welcome to the forums.
Very good concepts. Everyone who discovers and falls in love with the Prop comes up with these ideas. They have been discussed here a million time already.
My personal dream is a Prop III which has 8 (or more) 64 bit COGS, which allows extending the SRC and DST fields of instructions to 25 bits and allows for 32Mega LONG COG address space (if my calcs are correct). Not that a COG would have that much RAM but a lot more anyway.
Regarding item 1 & 2, Propeller II will have at least 128KB HUB memory and fast inter-COG communications.
Item 3 is desirable. I would also like to see on-board Flash.
One thing I would like to see later is a Propeller with an ARM Core+Flash. This has come up before.
I think Chip is probably interested in a vacation by now though.
(StefanL38, I love your avatar!)
I am happy to live with no eeprom on the chip. The fact that we have what was a large 32KB hub ram has proven to be a big point, along with the cogs.
But we all find that 2KB is too small for some things.
My dream Prop would be 512KB SRAM hub, 16 cogs with 1 cog having a supercog status that has more hub access cycles than the others. This would alleviate the small cog ram issue somewhat. Otherwise, 1 cog with 1KB bank switched cog ram of 8KB. 8 of these cogs would only have the counters of Prop1 (without VGA & TV options) but allow for input serial to parallel - so, in other words, 8 tiny cogs. Booting would be from (micro)SD card. And 64+ I/O pins, plus 32 internal I/O pins for intercog comms.
It would be nice if HUB memory were FRAM, then you have the advantage of RAM and FLASH, without doing a Harvard architecture like now.
That is all a lot to ask for, but I would expect that Chip won't leave things alone once the Prop 2 is golden, he'll immediately start thinking of things that he wanted to do in the Prop 2, but couldn't.
I suggested a small 32 or 64 cell CPLD be integrated so you could do some heavy glue in logic for really intensive I/O things instead of limiting the speed as a function of software.
It's all pie in the sky right now, the compromises that have been made to produce the Prop 2 are just, and based on all the factors, not just what we can see.