Measured delays through circuit. MafIn1Raw to MafIn1 is about 7.8 uSec. From MafIn1 to MafOut1 it's about 4.4 uSecs. Obviously the op amp circuit is introducing most of the delay, and the inverter is probably taking up most of the remaining 4.4 uSecs.
Screen captures off my logic analyzer with signals named on right. MafClampIn signal is active low. i.e. when low the circuit clamps MafOut1/2 to the last measured frequency of MafIn1/2, otherwise MafOut1/2 just follows MafIn1/2. It works as designed. You can see cases where he outputs need to be resynced up to the inputs when the clamp signal changes from clamp to follow.
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Here's the board setup: