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Need to sync timers, and match on count for one via polling/waiting — Parallax Forums

Need to sync timers, and match on count for one via polling/waiting

nmz787nmz787 Posts: 24
edited 2012-01-29 19:25 in Propeller 1
Basically I want two GPIO lines toggling at 50% duty, one will be 4Mhz, the other will be <=1khz, variable in 250uS increments so its edges always always correspond to a rising edge of the 4Mhz line

I need to set up the two PWM lines with the timers, then start them, sync them, then poll the <=1khz PWM line to see when it goes low... then I'll execute some code there.

Comments

  • Duane DegnDuane Degn Posts: 10,588
    edited 2012-01-18 10:52
    Is this the same project as this thread?

    Do you really need a 50% duty? A lot of devices don't really care about the duty cycle of a clock pulse. They'll have mininum and maximum times when different lines need to rise and fall.

    It might help if you post the datasheet of the device.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-01-18 14:07
    It won't be possible, with two autonomous counters, to have the edges line up exactly, unless the frequency of each is a power-of-two submultiple of the system clock frequency*. This is because NCO and NCO-driven PLL counters exhibit phase jitter when their frequencies deviate from those constraints. So, I'm with Duane. Tell us what part you're trying to interface and point us to a datasheet, so that maybe we can help with a less narrowly-defined problem.

    -Phil

    *Before Kuroneko jumps on this assertion, it's not quite that stringent, as long as frqb is related to frqa by a simple shift operation.
  • nmz787nmz787 Posts: 24
    edited 2012-01-18 15:17
    Duane Degn wrote: »
    Is this the same project as this thread?

    Do you really need a 50% duty? A lot of devices don't really care about the duty cycle of a clock pulse. They'll have mininum and maximum times when different lines need to rise and fall.

    It might help if you post the datasheet of the device.

    Yes same project, I couldn't find the minimum time for WAITCNT in assembly (though the SPIN version clearly states minimum is 281 or 381 cycles)... I think I'd be able to use that if it could respond in less than 20 cycles. The propeller manual also doesn't specify how quickly WAITPNE can respond... I thought of having a 4Mhz PWM looping back to a pin that was being sensed with WAITPNE, then toggling the lines manually

    The datasheet says the duty cycle doesn't matter on the variable period GPIO, but looks like 50% on the master clock (4Mhz) GPIO (though it doesn't mention that specifically)

    http://openspectrometer.com/datasheets/TCD1304AP.pdf
  • nmz787nmz787 Posts: 24
    edited 2012-01-18 15:38
    Phil Pilgrim (PhiPi) wrote: »
    It won't be possible, with two autonomous counters, to have the edges line up exactly, unless the frequency of each is a power-of-two submultiple of the system clock frequency*. This is because NCO and NCO-driven PLL counters exhibit phase jitter when their frequencies deviate from those constraints. So, I'm with Duane. Tell us what part you're trying to interface and point us to a datasheet, so that maybe we can help with a less narrowly-defined problem.

    -Phil

    *Before Kuroneko jumps on this assertion, it's not quite that stringent, as long as frqb is related to frqa by a simple shift operation.

    wait, what!? That seems like a big fault/limitation... am I wrong?
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-01-18 15:55
    It's not a fault. It's just the way NCO counters operate -- whether Propeller-based or otherwise. But I seriously doubt that it's going to make a difference in your app. First, I'll have to look at the datasheet to see what the CCD's setup and hold times are.

    -Phil
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-01-18 16:05
    Looking at the datasheet, are your two signals ΦM and ICG?

    -Phil
  • nmz787nmz787 Posts: 24
    edited 2012-01-18 20:58
    Phil Pilgrim (PhiPi) wrote: »
    Looking at the datasheet, are your two signals ΦM and ICG?

    -Phil

    Almost, the two that don't change are ΦM and SH... ICG is pulled low for 1 SH period, just before 1/2 mark of the first SH period (ICG goes low just before SH goes high, ICG comes high on rising edge of ΦM after ~1 SH period of time )
  • nmz787nmz787 Posts: 24
    edited 2012-01-19 00:19
    Phil Pilgrim (PhiPi) wrote: »
    It's not a fault. It's just the way NCO counters operate -- whether Propeller-based or otherwise. But I seriously doubt that it's going to make a difference in your app. First, I'll have to look at the datasheet to see what the CCD's setup and hold times are.

    -Phil

    I made a spreadsheet that's public of the times and frequencies of the 2^N value possibilities :
    https://docs.google.com/spreadsheet/ccc?key=0AkTsdtdxo56DdDFZb0EtU2JyY3l2am53b2o1b1ZKR2c

    I think that the values provided should be fine, at least for now (I don't know how much the exposure time will need adjusted, but the minimum is 10 microseconds)

    So how do I sync the clocks? I'm testing this code now: 
    ''Demonstration of NCO counter mode (100)
CON
_clkmode = xtal1 + pll16x
_xinfreq = 6_000_000
PUB NCO_single_ended_mode
' mode PLL BPIN APIN
ctra := 100_000 << 23 + 1 << 9 + 0 'Establish mode and APIN (BPIN is ignored)
frqa := $8000_0000 'Set FRQA so PHSA[31] toggles every clock
dira[0] := 1 'Set APIN to output
repeat 'infinite loop, so counter continues to run
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-01-19 09:05
    You won't be able to sync two clocks in Spin, due to the interpreter's hub-access uncertainty. It'll have to be done in PASM.

    -Phil
  • nmz787nmz787 Posts: 24
    edited 2012-01-19 22:35
    Phil Pilgrim (PhiPi) wrote: »
    You won't be able to sync two clocks in Spin, due to the interpreter's hub-access uncertainty. It'll have to be done in PASM.

    -Phil

    Do you have some pointers, I'm not sure how to go about syncing them
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-01-19 23:54
    Set up everything ahead of time except for the ctra and ctrb registers. You will start the counters in two successive instructions by assigning ctra, then ctrb. Assuming that phsa is initialized to zero, preset phsb to 4 * frqb.This will give it the head start it needs, since it gets started four clock cycles after the other counter. From there, the two counters should remain in phase assuming, as I mentioned above, that frqa and frqb are related to each other by a shift. I'd have to think some more about it, but that condition might be relaxed further to say that the higher frequency can be any even multiple of the lower one, if you want both edges of the lower frequency line up with edges of the higher one.

    -Phil
  • nmz787nmz787 Posts: 24
    edited 2012-01-29 19:21
    Phil Pilgrim (PhiPi) wrote: »
    Set up everything ahead of time except for the ctra and ctrb registers. You will start the counters in two successive instructions by assigning ctra, then ctrb. Assuming that phsa is initialized to zero, preset phsb to 4 * frqb.This will give it the head start it needs, since it gets started four clock cycles after the other counter. From there, the two counters should remain in phase assuming, as I mentioned above, that frqa and frqb are related to each other by a shift. I'd have to think some more about it, but that condition might be relaxed further to say that the higher frequency can be any even multiple of the lower one, if you want both edges of the lower frequency line up with edges of the higher one.

    -Phil

    Thanks, got it working just after you posted.

    So if the counter has 10 decimals left before overflowing, and FRQx adds 15, is the counter at 0 or 5 on the next clock cycle? I tried changing the FRQB to something that was just a multiple of FRQA and it didn't seem to work, but I didn't mess with it too much so I can't be sure I did it right (i.e. off by one, etc)
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-01-29 19:25
    nmz787 wrote:
    So if the counter has 10 decimals left before overflowing, and FRQx adds 15, is the counter at 0 or 5 on the next clock cycle?
    5.

    -Phil
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