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Correlation between external clock and propeller clock when using PLL — Parallax Forums

Correlation between external clock and propeller clock when using PLL

Andrey DemenevAndrey Demenev Posts: 377
edited 2012-01-09 17:03 in Propeller 1
When using external clock source and PLL, does the PLL's output phase matches external clock's phase?

Comments

  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-01-09 00:36
    What do you mean by "match" exactly? IOW, if you had a 5 MHz input to produce an 80 MHz system clock, how close, in nanoseconds (out of 12.5) would the rising edges of each have to be to match? OTOH, I'm not even sure what in means in real terms to be "in phase", since any external manifestation of the system clock will encounter some delay. IOW, how can you even know where the internal edges of the system clock occur? And, moreover, why does it matter?

    -Phil
  • RaymanRayman Posts: 14,849
    edited 2012-01-09 06:50
    I've wondered about that too...
    Are you trying to sync 2 Prop chips with a 5 MHz clock source or something like that?

    I imagine the PLL would be well sync'd, but there is sure to be some jitter...
  • Duane C. JohnsonDuane C. Johnson Posts: 955
    edited 2012-01-09 15:27
    The internal clock of the several props will be phase locked to common external oscillator.
    However, the individual phase angles will not be exactly the same, probably close but not the same.

    The only way to have them all be exactly the same would be to have a common external oscillator running at full speed, i.e. no PLL involved.

    Duane
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-01-09 15:47
    Regarding jitter, there should be very little, if any, assuming the driving clock is jitter-free. The issue with jitter in those PLLs driven from NCO counters is due to deterministic phase noise from the counters, combined with a short loop filter time constant, not from any jitter inherent in the VCO itself.

    -Phil
  • Duane C. JohnsonDuane C. Johnson Posts: 955
    edited 2012-01-09 16:26
    Phil;
    I think Andrey was not asking about jitter. He wanted to know if the separate clocks edges line up. Since the phase gain in the individual PLLs are differnt, especially in 16X mode, there will be significant phase differences in the 80MHz clocks. Sure, the frequency will be the same but the edges will not exactly line up.

    Duane
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2012-01-09 16:59
    Duane,

    My prior post was more in response to Rayman's post (#3). 'Just wanted to clarify the difference between the VCO's native phase noise (which should be minimal) and NCO-induced jitter, since the latter is such a hot topic in other threads.

    -Phil
  • jmgjmg Posts: 15,183
    edited 2012-01-09 17:03
    Andrey Demenev wrote: »
    When using external clock source and PLL, does the PLL's output phase matches external clock's phase?

    You would need to measure this.
    There are multiple issues here, working against you.

    The PLL lock times will differ, so what they consider as Zero time, will phase move from chip to chip & even each Power cycle..
    Software could help reduce this effect.

    Once locked, the Xtal-in to PinOut edge will be a combination of Chip delays, and PLL sync phase, and some of those will vary with temperature/batch/Vcc, - but it may be short term delays is all that matter to you ?

    So if this matters, your best bet may be to use a Sync pin across multiple parts, and that will define which time-slot everyone is in.
    Even there, not all devices might see the edge as being the same instant, but a phase-fractional delay on that sync, might help your yield ? (ie you move the actual edge away from the chips sampling aperture)
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