Cog questions
lardom
Posts: 1,659
From the datasheet cog ram is arranged as 496 general purpose registers plus 16 special purpose registers.
(496 * 32) and (16 * 32)
Cog ram is 2K
512 * 32 = 16,384 This doesn't equal 2K ram. What am I missing?
My second question is where does PASM reside?
(496 * 32) and (16 * 32)
Cog ram is 2K
512 * 32 = 16,384 This doesn't equal 2K ram. What am I missing?
My second question is where does PASM reside?
714 x 397 - 82K
353 x 238 - 24K
Comments
Note: it's only 496 longs, but everyone rounds up to 2K. Also COG RAM is a separate private memory area for each COG while HUB RAM (32K) is shared. However, the 496 longs are loaded from HUB RAM (or ROM in the case of the SPIN intepreter & bootloaders) by coginit/cognew. Once the coginit/cognew has been completed the RAM may be repurposed in many cases. PASM drivers may be less than 496 longs, but coginit/cognew always copies all 496 longs.
The cog memory is actually 512 longs (2K bytes), but the last 16 longs are treated specially. For those that are designated read-only (like INA and CNT), the special functionality is accessed when their address is used in the source field of an instruction. When the address is used in the destination field of the instruction (or used to fetch an instruction), the cog memory location is used. This is sometimes called "shadow memory" because it exists in the shadows cast by the special function registers. For special locations designated as read-write, they can be written (along with the special function registers) by using them in the destination field of an instruction, but you can't read them (except to execute them as instructions).
It looks like the PASM drivers are stored at a physical address in hub ROM and they are loaded into cog RAM from hub RAM.
I think I read that cog RAM is long addressable only. Does that mean PASM is limited to something less than 496 lines of code?
Yes, cog RAM is long addressable only.
You can always find a way to write more than 496 lines of code that will fit into a cog, but it has to come down to no more than 496 longs. You could have a table of byte values, one per line, packed 4 per long, for example.
I think I read that cog RAM is long addressable only. Does that mean PASM is limited to something less than 496 lines of code?[/QUOTE]
Yes and no. First, PASM has an extreme case of code/data duality. Each of the 496 32 bit "registers" may contain an instruction or data and it is completely possible (and in some cases required) to use data operations to modify instructions. So those 496 longs loaded by coginit/cognew will contain variables used by the PASM code. Thus the basic PASM program is no more than 496 longs in size. (Of course some data may be stored in HUB RAM, but it has to be copied to COG RAM before it can be operated on.) However there are two main methods to go beyond the 496 long limit (note: neither method is directly supported by the Propeller Tool).
The first method is overlays where chunks of code are copied into COG RAM as required. The copy requires time and therefore introduces latency. But once the code is copied into COG RAM it executes at full speed.
The second method is called LMM (large memory model). In this case the PASM code is stored in HUB RAM (or external RAM, in which case it's called XMM). Each instruction is copied to COG RAM and executed (with special handling for some instructions). This has a significant impact on execution speed but can allow for very large PASM programs (as might be generated by a C compiler).
"Where are the reserved words and rules stored?"
Furthermore, "If 496 longs are loaded into the cog, which is the limit, then where is the room to perform calculations?"
496 longs may not seem like a lot, but the Propeller's native instruction set is very efficient. Plus, the code in each cog has access to the hub's full 32K ROM and 32K RAM spaces for data. This is how the Spin interpreter works, BTW: the entire byte-code interpreter resides in those 496 longs of cog space and interprets the compiled Spin code as hub-resident data. So, you see, that amount of cog space is not as limiting as one might imagine at first blush.
-Phil
In opposite to "all"? other microcontrollers/microprocessors, the RAM the processor uses is used for calculations. In other architectures you always have to load values into a set of registers. Only those registers can be used for arithmetic/logical operations.
Each processor has it's own machine language. There is no ONE common language for all processors on machine level. The machine language is directly implemented in the hardware one way or the other. The bitpattern of a machine instruction directly or indirectly tells the hardware what to do. What I mean with indirectly is, that some microprocessor architecures have some microcode which internally runs.
"Principles of Computer Architecture by M. Murdocca and V. Heuring"
PS: My set of PDFs has 10 chapters + two appendixes