USB 3.0 Will Let Processors Communicate with Each Other:SSIC (Super Speed Inter-Chip)
Bob Lawrence (VE1RLL)
Posts: 1,720
USB 3.0 Will Let Processors Communicate with Each Other SSIC (Super Speed Inter-Chip) interface
November 19, 2011 | Posted by admin
The Universal Serial Bus 3.0 SuperSpeed interface is about to gain a new role, one that will be different from enabling communications between storage units and host products.
Not too different, though, since intercommunication is still what it will accomplish, only between the processors of a single device.
USB-IF and the MIPI Appliance have partnered to make the SSIC (Super Speed Inter-Chip) interface.
Chip interconnects have already started to limit what smartphones and tablets can do, since the various chipsets have to settle for GPIO, HSIC, etc.
Needless to say, their capabilities arent even close to what, say, the PCI Express of a PC can do.
USB 3.0 will be used for very short PCB traces and should be power efficient enough and easier to implement than PCI Express.
It will have x1, x2 and x4 lanes, but it isnt clear what bandwidth each of those lanes will have.
:cool:
Source: http://www.endblock.info/usb-3-0-will-let-processors-communicate-with-each-other.html
November 19, 2011 | Posted by adminThe Universal Serial Bus 3.0 SuperSpeed interface is about to gain a new role, one that will be different from enabling communications between storage units and host products.
Not too different, though, since intercommunication is still what it will accomplish, only between the processors of a single device.
USB-IF and the MIPI Appliance have partnered to make the SSIC (Super Speed Inter-Chip) interface.
Chip interconnects have already started to limit what smartphones and tablets can do, since the various chipsets have to settle for GPIO, HSIC, etc.
Needless to say, their capabilities arent even close to what, say, the PCI Express of a PC can do.
USB 3.0 will be used for very short PCB traces and should be power efficient enough and easier to implement than PCI Express.
It will have x1, x2 and x4 lanes, but it isnt clear what bandwidth each of those lanes will have.
:cool:
Source: http://www.endblock.info/usb-3-0-will-let-processors-communicate-with-each-other.html