Can a Schmitt trigger and Delta sigma ADC be implemented on the same two pins?
Capt. Quirk
Posts: 872
I was reading the schmitt trigger app-note tonight to see if it would work as a comparator
for a zero-cross detector on my bldc controller project. The circuit reminded me of the delta
sigma circuit, with the exception of the two capacitors used by the adc.
Since I need a comparator for the zero cross detection and an adc for the bmef;
can I just use the delta sigma circuit, and control the circuit with Pasm to provide
the comparator or adc functions using the same cog?
If so, is the adc resistor values, or resistor-capacitor combination flexible enough to make this work?
Note: Is the delta sigma adc fast enough to work as a comparator? The appnote specs suggest it is.
Since ZC detection occurs after 30% to 50% of the rpm range, its timing should be predictable enough
to find a sample time frame to catch the zero cross. This was my original intent.
Thanks
Bill M.
for a zero-cross detector on my bldc controller project. The circuit reminded me of the delta
sigma circuit, with the exception of the two capacitors used by the adc.
Since I need a comparator for the zero cross detection and an adc for the bmef;
can I just use the delta sigma circuit, and control the circuit with Pasm to provide
the comparator or adc functions using the same cog?
If so, is the adc resistor values, or resistor-capacitor combination flexible enough to make this work?
Note: Is the delta sigma adc fast enough to work as a comparator? The appnote specs suggest it is.
Since ZC detection occurs after 30% to 50% of the rpm range, its timing should be predictable enough
to find a sample time frame to catch the zero cross. This was my original intent.
Thanks
Bill M.
Comments
You could possibly use the delta-sigma for this purpose, but probably not combined with the comparator. Delta-sigma uses negative feedback to do fine but relatively slow charge balancing, while the comparator uses positive feedback to get quick snap action. The resistor values required are likely to be quite different for those two purposes. The ratio of feeback resistor to input resistor for the comparator will be high, to set a narrow hysteresis range of a few tenths of a volt. On the other hand, the ratio of resistors for the delta-sigma is likely to be close to unity, to scale the input into something like 0 to 3.3 volts. I'm not saying it can't be done, just that is is a quantitative problem around the values of those resistors.
Back in 2006, Peter Verkaik demonstrated a way to calculate those values for the SX. I finally
found it this morning, and I will find out if it is possible.---Thanks.
If the comparator is just for Zero crossing, and does not need high speed, then a short ADC cycle could suffice.
The SDM ADC averages across multiple cycles anyway, so you could extend the precision by averaging for back EMF.
Note that an ideal SDM ADC should have an integrator, a simple RC filter weights away from LSB energy, so there is a limit to how
much Software total/average can give you.