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SPI flash goes to Quad-DDR, 66MB/s — Parallax Forums

SPI flash goes to Quad-DDR, 66MB/s

jmgjmg Posts: 15,185
edited 2011-10-01 09:50 in Propeller 1
Spansion have new SPI flash, that does DDR reads, so gets 66Mbytes/sec, from a 66MHz clock on a Quad interfaced 8 pin package.

http://www.eetimes.com/electronics-products/electronic-product-reviews/memory-products/4228497/Spansion-claims-world-s-fastest-serial-flash-memory

http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf

Hopefully, the Prop II will have the simple hardware-level interface needed to take full advantage of this memory bandwidth ?

A small package, with flexible FLASH sizes, and 66Mbytes / sec, is a natural complement.

Comments

  • RaymanRayman Posts: 14,867
    edited 2011-09-30 13:08
    That would be a real winner!
  • jazzedjazzed Posts: 11,803
    edited 2011-09-30 13:26
    It would make a difference when used by a micro that's fast enough.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2011-09-30 14:16
    jmg wrote:
    Hopefully, the Prop II will have the simple hardware-level interface needed to take full advantage of this memory bandwidth ?
    Hopefully not, if it means wasting silicon on a dedicated protocol engine. Memory access protocols go obsolete way quicker than the Prop I or II ever will.

    -Phil
  • jmgjmg Posts: 15,185
    edited 2011-09-30 15:09
    Phil Pilgrim (PhiPi) wrote: »
    Hopefully not, if it means wasting silicon on a dedicated protocol engine. Memory access protocols go obsolete way quicker than the Prop I or II ever will.

    ? SPI is already much older then Prop 1, and it is clearly not going away.
    DDR is also older than Prop 1, so these ideas are not fashion, they are fundamental.

    It does not need a large silicon area, just a serialiser, and maybe some simple DMA.

    Given Prop II does NOT have any FLASH code memory itself, giving smarter access to extenal flash would seem a no-brainer. (to me)
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2011-09-30 16:42
    A protocol-agnostic input serializer -- something like the reverse of waitvid -- would be great, and I expect to see it implemented in the Prop II. But, beyond that, no. Don't forget, anything that's protocol-specific has to be replicated across all the chip's I/O pins. It's not like a PIC or AVR, where only certain pins support certain peripherals.

    -Phil
  • RaymanRayman Posts: 14,867
    edited 2011-09-30 16:44
    We really do need that. I think somebody called it a deserializer. I remember Saphiea discussing this with Chip. I sure hope it's included in Prop 2.
  • RaymanRayman Posts: 14,867
    edited 2011-10-01 05:18
    Another option that would make things faster is a wrlong and rdlong that automatically increases the source or destination register by 4...
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2011-10-01 07:39
    IIRC, index autoincrement will be a Prop II feature, as originally requested by Bill Henning to make LMM more efficient.

    -Phil
  • jazzedjazzed Posts: 11,803
    edited 2011-10-01 09:50
    Phil Pilgrim (PhiPi) wrote: »
    IIRC, index autoincrement will be a Prop II feature, as originally requested by Bill Henning to make LMM more efficient.

    -Phil
    And as requested by many others for other uses! :)

    There are serializer/deserializer (SERDES) instructions (list posted previously), but i have no idea how to use them.
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