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Why No Indirect Addressing ? — Parallax Forums

Why No Indirect Addressing ?

pjvpjv Posts: 1,903
edited 2011-09-16 12:58 in Propeller 1
Hi All;

Not a complaint, because I love the Prop, but just a curiosity here;

I know it is part of the design philosophy, but what would be the reasoning for the absense of indirect addressing on the Prop ?

While one can, somewhat painfully, work around it, it makes the code much messier, and adds quite a performance hit.

Most other processors have this capability; why not the Prop?

Cheers,

Peter (pjv)

Comments

  • BeanBean Posts: 8,129
    edited 2011-09-15 13:55
    My guess is that it is because the COG ram is so small (only 512 longs).

    Bean
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2011-09-15 14:00
    Indirect addressing would screw up the four-stage pipeline, because it would entail an extra cog memory access.

    -Phil
  • Mike GreenMike Green Posts: 23,101
    edited 2011-09-15 14:23
    There is hub memory indirect addressing on RDxxxx and WRxxxx. You could use macros to implement indirect addressing using the usual instruction modification given that indirect addressing would slow down any instruction given the four-stage pipeline. That would be quite a bit slower and would use additional memory. Regardless, there are no bits available in the instruction to specify it.
  • ericballericball Posts: 774
    edited 2011-09-15 18:52
    Finally, where would you squeeze the indirect address flag it into the 32 bit opcode? 6 bit opcode (64 opcodes, although hubops cheat), 9 bit source, 9 bit destination (512 registers), 4 bit condition code, 4 bit flags (immediate, write, carry, zero) = all 32 bits used.

    Yes, trying to use COG RAM as an array is a pain in the behind. However, it's typically not worth the effort over using HUB RAM (especially for anything other than 32 bit ops). Count you cycles and your instructions.
  • AribaAriba Posts: 2,690
    edited 2011-09-15 20:34
    ericball wrote: »
    Finally, where would you squeeze the indirect address flag it into the 32 bit opcode? 6 bit opcode (64 opcodes, although hubops cheat), 9 bit source, 9 bit destination (512 registers), 4 bit condition code, 4 bit flags (immediate, write, carry, zero) = all 32 bits used...

    It can be made like in the early PICs: with 2 special purpose registers, i.e. called INDRW and INDPNTR. If you read from, or write to the register INDRW you access in reality the register with the address in the INDPNTR. This Pointer register can be modified before or after the IND access. IMHO this needs also no additional pipeline stage only an additional Multiplexer.

    I think the Prop2 will have something like this.

    Andy
  • jazzedjazzed Posts: 11,803
    edited 2011-09-15 20:49
    Indirect addressing by itself has limited usefulness without an auto increment or decrement on the index.
  • Mark_TMark_T Posts: 1,981
    edited 2011-09-16 12:58
    Ariba wrote: »
    It can be made like in the early PICs: with 2 special purpose registers, i.e. called INDRW and INDPNTR. If you read from, or write to the register INDRW you access in reality the register with the address in the INDPNTR. This Pointer register can be modified before or after the IND access. IMHO this needs also no additional pipeline stage only an additional Multiplexer.

    I think the Prop2 will have something like this.

    Andy

    Bit ugly and non-orthogonal - Isn't the Prop a RISC design? Until someone's written a compiler back-end I don't think they should be allowed to design an instruction set! [ having said that I do enjoy recreational use of the MUXC/Z instructions ;) ]
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