UPENE: Chips presentation on Prop II
Cluso99
Posts: 18,069
Wow! This is going to be some chip.
The I/O capability is spectacular. What it will be able to do (without cog intervention too) is mind-blowing.
Unfortunately a lot of audio interruptions due to bandwidth. Hopefully someone there may have recorded the presentation on a phone???
Thanks to John for doing what he could to keep the audio running as much as he did. Super effort John!
The I/O capability is spectacular. What it will be able to do (without cog intervention too) is mind-blowing.
Unfortunately a lot of audio interruptions due to bandwidth. Hopefully someone there may have recorded the presentation on a phone???
Thanks to John for doing what he could to keep the audio running as much as he did. Super effort John!
Comments
Chip was great to talk to in small groups during the day. While I was talking with him, he went onto some very interesting detail as to how the texture mapping will work and some of the details of the I/O pin features. I don't really want to regurgitate any details in case I got them wrong or misunderstood or misrepresent. Chip is very interesting to talk to about a myriad of topics!
Beau was there also but I didn't get to talk to him. I'm sure either Beau or Chip could provide a "State of the Prop II" update if we're nice!
I think a couple of folks may have been recording Chip's session with their phones.....they'll need to chime in.
During his "official" presentation, he did go over timelines and discussed the changes that have had to been made due to engineering and/or fabrication limitations discovered as they iterate through the process. He did discuss the I/O pin capabilities and often said the pins can do such and such a feature and then added "freeing up the COG for other work" - this all sounded very interesting and exciting.
I do this for the fun and adventure and not profit or professional gain, so my perspective is different than many of you "professional" propheads. My tolerance for feature changes and timeframe slips is probably a bit greater.
I was very impressed by the features presented and Chip was very inspiring!
I think the capabilities are pretty much as we already know. The impressive thing for me was how far they have progressed with optimising the logic to get the speed back to where we'd like it (160MHz). At one point they mentioned it was looking as bad as 40MHz but they've been steadily refining from what I understood.
They asked whether we'd prefer 100MHz operation with 3-clk branches(jumps) vs 160MHz with 5-clk branches - to me this is a no brainer (30nsec vs 31.25nsec but 160MHz straight line speed), but perhaps I'm missing some vital information as to why 100MHz might be preferable.
Timeline, I think there is a lot going on and its probably hard to see what the critical path is right at the moment. Whenever it comes out its going to be awesome...
An important association here, is the counter speeds.
So long as the counters can Run/Capture at the 160MHz, then it is a no-brainer. It is important to not have some small part of core operation (like jumps) pull down the Clock speed of the whole system.
I hope they are also allowing for faster counters, and an optionally slower core - a few micros are starting to offer this, and it will become more and more standard.
ErNa