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Propeller as heterodyne for DC transceiver (was Generating 30 MHz quadrature) — Parallax Forums

Propeller as heterodyne for DC transceiver (was Generating 30 MHz quadrature)

Andrey DemenevAndrey Demenev Posts: 377
edited 2011-08-22 16:48 in Propeller 1
I need to generate 2 square waves with 90° phase shift. The obvious way is to setup 2 counters in NCO mode with $4000_0000 difference in initial PHSx value. But this would only work for frequencies up to FCLK/4. I need 30 MHz output, and that would require 120 MHz clock. Way too much.

Another way would be using 60 MHz system clock, setting up a counter in video mode with 120 MHz pixel clock, an using WAITVID. But this wastes a cog.

Am I missing a way to generate 30 MHz quadrature using counters only, without software support?

Comments

  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2011-08-20 21:36
    Andrey,

    You can do what you want by using a PLL counter mode. Here's an example:
    CON
    
      _clkmode      = xtal1 + pll16x
      _xinfreq      = 5_000_000
    
      I_PIN         = 0
      Q_PIN         = 1
    
    PUB  start
    
      frq0 := frq_val(30_000_000 / 4)                       'Compute frqa and frqb.
      phsb0 := (frq0 << 2) - $1000_0000                     'Phsb lags phsa by $4000_0000 (>> 2 for PLL x4)
                                                            'Add frq0 x 4, since frqb is written four clocks later.
      cognew(@iq_freq, 0)
    
    PRI frq_val(frq) : r
    
    '' Compute the required value of frqx to obtain the frequency frq.
     
      repeat 32
         frq <<= 1
         r <<= 1
         if frq => clkfreq
            frq -= clkfreq
            r++
    
    DAT
    
                  org       0
    iq_freq       mov       dira,dira0
                  mov       ctra,ctra0
                  mov       ctrb,ctrb0
                  mov       phsb,phsb0
                  mov       frqa,frq0
                  mov       frqb,frq0
                  jmp       #$
    
    dira0         long      1 << I_PIN | 1 << Q_PIN
    ctra0         long      %00010 << 26 | %101 << 23 | I_PIN    'PLL mode: NCO freq x 4
    ctrb0         long      %00010 << 26 | %101 << 23 | Q_PIN
    frq0          long      0-0
    phsb0         long      0-0
    

    -Phil
  • Andrey DemenevAndrey Demenev Posts: 377
    edited 2011-08-20 21:59
    Phil, this method has one weakness : phase shift between PLL's VCO output and system clock depends on VCO's reaction to phase comparator's output. Although one can expect that CTRA and CTRB PLLs have very close parameters, they are not identical.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2011-08-20 22:18
    Once the PLLs are locked, the only phase error would come from unequal delays in the phase comparators themselves, which I would expect to be minimal.

    I would suggest trying it anyway and, if you can, measure the phase difference between the two outputs. This is the method I used to generate LO inputs to the I and Q mixers in my direct-conversion shortwave receiver experiment, and it seemed to work okay.

    If the potential for error still bothers you, just output the 120MHz signal and use external logic to form the quadrature signals. Whatever method you use, though, your biggest problem will be phase jitter, if you want clean signals, not average differential phase error.

    -Phil
  • Andrey DemenevAndrey Demenev Posts: 377
    edited 2011-08-20 22:36
    Once the PLLs are locked, the only phase error would come from unequal delays in the phase comparators themselves, which I would expect to be minimal.

    I don't understand this statement.

    In my understanding, in most general, PLL structure looks like this:

    pll.png


    PLL is locked, when output voltage from phase comparator is such that VCO's output freq equals F0. Since phase comparator's output is proportional to pahse difference between VCO and F0, phase shift between VCO and F0 depends on F0. But since VCOs are not identical, each one may need different voltage (read: phase shift) to produce F0 at VCO's output
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  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2011-08-20 23:08
    The voltage that controls the VCO is not instantaneously proportional to the phase difference. The lowpass filter interposed between the two acts as an integrator. When the input and output phases differ in one direction, the VCO voltage gets bumped up a little; in the other direction it gets bumped down. When there is no difference between the two phases, no correction voltage up or down is applied to the integrator, and its output voltage does not change. Between two locked PLLs the integrated VCO voltage may well be different to produce the same frequency, but that has no bearing on the phase relationship between their inputs and outputs which, at lock, is governed only by logic delays in the phase detector.

    -Phil
  • jmgjmg Posts: 15,185
    edited 2011-08-20 23:25
    Another way would be using 60 MHz system clock, setting up a counter in video mode with 120 MHz pixel clock, an using WAITVID. But this wastes a cog.

    Am I missing a way to generate 30 MHz quadrature using counters only, without software support?

    If you want quadrature, you will mean without jitter, and exactly 90.00' phase ?
    Note that 90' at 30MHz is 8.33333'ns - so unless you can think of a way to generate exact 8.333ns delays, you will need a clock of 120MHz.

    If you can tolerate "almost 90' ", then some tricks with opposite clock edges may be possible.
  • Andrey DemenevAndrey Demenev Posts: 377
    edited 2011-08-21 01:12
    Here is a simple test that proves that you can not rely on PLL's phase
    CON
    
      _clkmode      = xtal1 + pll16x
      _xinfreq      = 5_000_000
    
      I_PIN         = 0
      Q_PIN         = 1
    
    PUB  start
    
      frq0 := $8000_0000 >> 3
      cognew(@iq_freq, 0)
    
    DAT
    
                  org       0
    iq_freq       mov       dira,dira0
                  mov       ctra,ctra0
                  mov       ctrb,ctrb0
                  mov       dira0, cnt
                  add       dira0, delay
                  waitcnt   dira0, #0
                  mov       frqa,frq0
                  mov       frqb,frq0
                  jmp       #$
    
    dira0         long      1 << I_PIN | 1 << Q_PIN
    ctra0         long      %00010 << 26 | %000 << 23 | I_PIN
    ctrb0         long      %00010 << 26 | %000 << 23 | Q_PIN
    frq0          long      0-0
    delay         long      1000000
    
    

    CTRA and CTRB are set up to output same frequency, each using its own PLL. Frequency was set to minimum (80 MHz VCO, 128 PLLDIV) cause my scope has low bandwidth.

    To observe phase difference, I made a simple resistor network. Tho-channel scope would work better, but I do not have one. Each time I press Reset button, I see a different waveform - obviously phase of PLL depends on nothing but phase of the moon and bananas cost at Barneo.
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  • Andrey DemenevAndrey Demenev Posts: 377
    edited 2011-08-21 01:24
    jmg, I need exactly 90 degrees. Clock freq can be adjusted as needed.

    In fact, I am exproling usage of propeller as a heterodyne for direct conversion receiver, with clock frequency produced by external VCO
  • kuronekokuroneko Posts: 3,623
    edited 2011-08-21 01:38
    CTRA and CTRB are set up to output same frequency, each using its own PLL. Frequency was set to minimum (80 MHz VCO, 128 PLLDIV) cause my scope has low bandwidth.
    That's self-inflicted damage. The phase is stable up to /16, everything below is random.
    • PLL output is sync'd to the rising edge of the feeder NCO (starting with the low half of the cycle). Note that /32, /64 and /128 can lock to any rising edge (relative to NCO start), e.g. /128 can lock to 8n+0 .. 8n+7 meaning that starting a PLL in two different cogs will - despite NCOs being in sync - not necessarily sync the PLL output.
  • jmgjmg Posts: 15,185
    edited 2011-08-21 02:09
    jmg, I need exactly 90 degrees. Clock freq can be adjusted as needed.

    In fact, I am exproling usage of propeller as a heterodyne for direct conversion receiver, with clock frequency produced by external VCO

    If you have an external VCO, why not simply create the Quad signals as well - it's only 2 FipFlops.
  • Andrey DemenevAndrey Demenev Posts: 377
    edited 2011-08-21 02:30
    kuroneko, thanks! That gives me some hope :)

    I am renaming this topic, to not open a new one.

    Recently, some interest has been shown in using the Prop in radios using direct conversion techniques, mostly thanks to Phil's experiments with DSP. I already mentioned that this was the reason I started to learn Propeller. With Phil's FIR filters, my dreams are getting closer. But I would like to go further, and use as much of Prop as possible.

    A common approach in direct conversion transceivers' mixers is to generate a frequency 4x higher that working freq, and use counters and/or shift registers to generate quadrature sequence for the mixer. And common problem here is that ICs used (74AC series) are working at frequencies close to their limit (almost 120 MHz for 10 meters ham band). This makes the phase shift differ from 90 degrees, degrading transceiver's performance. There are methods to reduce this problem, like applying DC bias to counters' inputs, but this is frequency-dependent and not reliable.

    My idea was to use a microcontroller to generate a relatively low frequency (20-50 kHz) as a reference for external PLL using DDS technique, feed the PLL's output to Propeller's clock, and use the prop to output quadrature signals for the mixer. Since Propeller's outputs can change their state synchronously, there are big chances to achieve very precise 90 degrees phase shift for the mixer, regardless of frequency.

    My concern here is that I would need to use PLLs for both Propeller clock and counters, and how this would affect the spectrum. We know that when generating frequencies that are not CLKFREQ divided by a power of 2 introduces lots of phase jitter. This should not be a problem in my approach though, since DDS output with a proper filter can be of any frequency. What concerns me more is how clean is Propeller's PLLs' signal, even when using NCO set up with a power of 2?
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2011-08-21 08:50
    Andrey,

    The approach I plan to use is to build a superhet instead of a DC receiver. The IF would be 10 MHz (or 1/8 of the system clock frequency, whatever that happens to be). The mixer would be an SA612 whose sinewave oscillator would be controlled in a FLL/PLL feedback loop by the Prop using DUTY mode output and a varactor. This accomplishes three things:
    1. Because the LO is a sinewave, you don't get spurious mixer products (i.e. images) from LO harmonics.

    2. Additional pre-detector gain and selectivity can be had with a simple IF amplifier, along with a lattice filter which uses the same crystals that set the Propeller's system clock frequency.

    3. The I/Q clocks in the detector stay at one stable, jitter-free frequency.

    -Phil
  • LawsonLawson Posts: 870
    edited 2011-08-21 08:52
    Just a quick note on logic ICs. I've used 74LVC at 5v when I wanted the ultimate speed CMOS discrete components could provide. (some of the 1.8v parts as fast or faster but hard to find. ECL is lots faster but a hot can of worms. ) While LVC is specified for 3.3v operation it has the same absolute maximum voltage as AC or HC of 7 volts so it's safe to run at 5v. Haven't looked at this in a while but I think the LVC should be 30-50% faster than AC parts at the same voltage.

    Anywho, good luck with all this. It's a lot of fun reading about what smart people can get the Prop to do.

    Lawson
  • Duane C. JohnsonDuane C. Johnson Posts: 955
    edited 2011-08-21 09:01
    The best way to eliminate skew between the outputs of either FF or shift register Quadrature generation is to add a fast clocked D type register.

    This register de skews the variance and noise of the counters. Yes, there will still be a variation in the propagation delay in the register. However, this delay is, mostly, not frequency dependent and can be tweaked out using a simple RC delay.

    I have done this and the 90 deg characteristic was maintained over the full frequency range.

    Duane
  • Andrey DemenevAndrey Demenev Posts: 377
    edited 2011-08-21 09:07
    Phil, superheterodynes also have their problems, and proper IF selection is important. I personally currently have no interest in superhet radios, I like the beauty of DC radio. Anyway, this thread is not about superhet vs DC :)
  • potatoheadpotatohead Posts: 10,261
    edited 2011-08-21 09:14
    This is a thread I will follow with interest. I love radio, and have not yet done software radio.

    Please explain the beauty of DC as opposed to a super-het. I am just curious at this point. Not a debate, just idle curiosity. I think I understand what a poor IF choice is. 950Khz, for example on AM is a bad call, as it's right on top of one frequency allocation in the US. A station broadcasting there may see reduced quality, in the form of receiver artifacts at that frequency, for example. Are there others?
  • jmgjmg Posts: 15,185
    edited 2011-08-21 18:10
    Lawson wrote: »
    Just a quick note on logic ICs. I've used 74LVC at 5v when I wanted the ultimate speed CMOS discrete components could provide. (some of the 1.8v parts as fast or faster but hard to find. ECL is lots faster but a hot can of worms. )

    The NXP 74AUP series claim 550MHz speeds on their flip flops, so they could be a good compact choice, with low skews. 2 x 1G74's would give balanced quadrature signals
  • Andrey DemenevAndrey Demenev Posts: 377
    edited 2011-08-22 01:09
    I have run a simple test to see how Propeller would perform as a heterodyne. I do not have equipment to measure the spectrum of high frequencies directly. So I made a crystal oscillator tuned to about 5005.5 kHz, and fed it to a mixer (74HC4053) with Propller-generated 5 MHz square wave. The product was passed through a simple LPF, and sampled with computer's sound card.

    spectrum.jpg


    The spectrum looks pretty clean, especially taking it account that I clearly see on the scope that the product signal degrades when I connect the sound card. That said, the spectrum of the Propeller's PLL is not as bad as one could expect. Obviously, such a heterodyne would never be as good as a good VFO or "real" synthesizer, but I think it would be sufficient for a mid-class transceiver.

    I envision the following possible structure of a receiver:

    dcrx.png


    The frequency is synthesized with a PLL, where instead of a divider, a DDS generator is used. Phase comparator works at frequency of 32 kHz. That is high enough for fast PLL lock, and low enough to obtain pure waveform with DDS. Quadrature signals for the mixer are generated by Propeller's counters or video generator. The VCO should cover the range of 28..32 MHz for 160, 80, 40, 20 and 10 meters bands. WARC bands would require additional VCOs though.

    Phase comparator can be built using Propeller itself.

    Another Propeller chip would be used to demodulate the quadrature signals.

    That's my plan :) Not sure how it will go, or if I ever finish (or even start :)) implementing it. Anyway, I am open for discussion and suggestions.
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  • Mark_TMark_T Posts: 1,981
    edited 2011-08-22 16:48
    Andrey,

    The approach I plan to use is to build a superhet instead of a DC receiver. The IF would be 10 MHz (or 1/8 of the system clock frequency, whatever that happens to be). The mixer would be an SA612 whose sinewave oscillator would be controlled in a FLL/PLL feedback loop by the Prop using DUTY mode output and a varactor. This accomplishes three things:
    1. Because the LO is a sinewave, you don't get spurious mixer products (i.e. images) from LO harmonics.
    -Phil

    Surely that's only the case if the mixer is a precision multiplying mixer - which is not normally done at RF is it?
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