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(Conept) Distributed Computer, Prop Moderated. — Parallax Forums

(Conept) Distributed Computer, Prop Moderated.

davidsaundersdavidsaunders Posts: 1,559
edited 2011-06-22 18:34 in Propeller 1
Concept: Distributed using propellers to moderate inter MPU communication.

I am posting this concept just in case any one else wishes to give it a go. I have read many many threads about distributed computing on these forums, so some one may be interested.

I have had this idea floating around for some time now.

The core concept is to use groups of 3 W65C816S MPUs with one Prop connected to the low 4 bits of the address lines and the low 4 bits of the data bus of each MPU for inter MPU com and some extras, to be more realistic probably multiplex the Address and Data bus bits into the Prop, though each groups prop would use a high speed serial link to communicate with the previous and next groups Prop allowing an unlimited number of MPUs in a ring. I have been looking at various ways to do this and it is just a concept at this time.

Another way would be to directly attach all 24 lines and use 1 prop for up to 8 MPUs, by multiplexing the IO to the MPUs 8 ways using latches. This is probably more doable and will probably be the method I use if I ever have the time to do this. Either way I intend to end up with a system with 128 W65C816S MPUs at 20Mhz and 1 extra Prop for KB/Mouse/Video/External serial.

Being as it is reasonable to expect an average of 5Mips from each W65C816S this would give a total capability of 640Mips, and being an expandable ring architecture this could be increased (1024 MPUs = 5.12 GIPS).

Comments

  • mindrobotsmindrobots Posts: 6,506
    edited 2011-06-22 11:00
    This sounds interesting. I'm trying to picture where the W65C816S address space (RAM) sits in this picture. I keep picturing a star configuration with the Propeller in the center acting as a point-to-point switch between the 65816's. I don't think that's what you meant but I can't shake the image from my tiny brain.

    Rick
  • LeonLeon Posts: 7,620
    edited 2011-06-22 12:39
    Many years ago Meiko built massively-parallel computers using transputers and Intel 860 processors. The transputers handled the comms between the processors with their link engines. Parsytec also built similar systems.
  • davidsaundersdavidsaunders Posts: 1,559
    edited 2011-06-22 18:21
    mindrobots:
    Think of a setup where in the Propeller is set to a fairly small address range some where around $EFF100 in the W65C816S memory map, and it multiplexes between the 6 W65C816S MPUs, each MPU would have its own 12MB of ram using a 8MB (64M x 8), a 2MB (16M x 8) SRAM, and a 2MB (16M x 8) EEPROM, and then have a shared 4MB window consisting of a 4MB SRAM and the Propeller (the uper 4KB of this being used fr the Prop), and each of these sets being able to communicate with two others with a high speed inter Prop serial connection (so that a ring is formed) needless to say there would be a need for some additional logic.
  • mindrobotsmindrobots Posts: 6,506
    edited 2011-06-22 18:34
    Thank you! That helps a lot!
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