All I have is an informed guestimate. cog N >> pin P >> cog M round trips suggest that timing is somehow symmetrical (for want of a better word). cogs 0..3 are better used with pin groups 0 and 1, cogs 4..7 favour groups 2 and 3. This ties in with the OR-chain schematic in the datasheet (9.5 Cog and I/O Pin Relationship). Looking at a QFP prop, pin 0 is located in the middle of a pin group (cw from chip marker). If you align that location - big assumption here - with the top/middle pin of the die then you'll end up with cog 0 left and cog 7 right (in a linear fashion).
Note, the delay effect is only visible above 52MHz (I didn't have any other crystal to get closer to 80MHz, most likely 64MHz will still be OK). At standard operating frequency (80MHz) [thread=127653]pin synchronisation[/thread] is a no-go.
I'm seeing differences between the cogs, which I think is explained mostly by the OR chain difference, but partially due to other factors too.
With regard to pins, I gather the double bond pad connections are Vss or Vdd. The left and right sides of the die image each have two single bond pads in between the Vss and Vdd pairs (BOEn/Reset, and XO/XI). I was assuming the left pin pair, which are more closely spaced and somewhat "symmetric" in their metal connection (on the Flylogic image, wrt the right hand pair), might be the XO and XI, but this would go against your suggestion above. I think I'll go with your suggestion and see how far it gets me, but keep in the back of my mind it may be 180 degrees out.
Thanks for the pin syncronisation link, very interesting reading.
Ok. I think I more or less verified the cogs are laid down in a linear fashion, 0 thru 7. This diagram is an averaged response of cogs 1 through 6 (labels A through F) to exactly the same pin (P12) being toggled, though it gets a bit murky in the middle with C D and E (cogs 3-5) being harder to distinguish.
Dave, it was really a qualitative test averaged statistically over a large number of cycles. I would hate to have to work back to work out what it means in quantitative terms.
Comments
Note, the delay effect is only visible above 52MHz (I didn't have any other crystal to get closer to 80MHz, most likely 64MHz will still be OK). At standard operating frequency (80MHz) [thread=127653]pin synchronisation[/thread] is a no-go.
I'm seeing differences between the cogs, which I think is explained mostly by the OR chain difference, but partially due to other factors too.
With regard to pins, I gather the double bond pad connections are Vss or Vdd. The left and right sides of the die image each have two single bond pads in between the Vss and Vdd pairs (BOEn/Reset, and XO/XI). I was assuming the left pin pair, which are more closely spaced and somewhat "symmetric" in their metal connection (on the Flylogic image, wrt the right hand pair), might be the XO and XI, but this would go against your suggestion above. I think I'll go with your suggestion and see how far it gets me, but keep in the back of my mind it may be 180 degrees out.
Thanks for the pin syncronisation link, very interesting reading.
Just look for the silkscreen on the die Haha! Right beside his signature!