Lon Glazner's High Power Bridge
JimG
Posts: 84
Lon did and article in Nuts adn Volts in conjunction with Parallax titled Stamp-controlled High-power H-bridge. It was Column #52, in teh August 99 issue. Can anyone help me with this circuit a littl ebit? I realize it is old but I am interested in it. I hae it build but it doesn't work. I AM NOT using the Stamp with it yet. I am just connecting the appropriate pins to the + or - side of the chip power supply to simulate the Stamp. I have attached the article.
Thanks,
Jim
Thanks,
Jim
Comments
Jim
You still haven't described what happened that you describe as "doesn't work".
1) AHO[Q4] and BLO[Q3] on
or
2) BHO[Q1] and ALO[Q4] on.
The objective is Q2 and Q3 for one direction, Q1 and Q4 for the opposite.
Your H-Bridge.pdf shows you with ALI and BLI hardwired to + and BHI and AHI hardwired to GND.
You need to have AHI and BLI on or BHI and ALI on.
If the A highside is on, it needs to have the B lowside on, too.
Conversely, with the B highside on, the A lowside should be on with it.
Jim
Not in conformance.
PE -- The IC's outputs aren't right.
I'd disconnect the FETs from the IC till I got those IC outputs to come right.
Having had both A-side FETs on together (or both B-side) didn't do them a world of good either.
I am not sure what you are referring to?
JIm
Jim
"IOC", "IOF", now you've got me. Not important.
You need, as I see it, to make sure that the IC outputs are appropriate, given the respective inputs. So, "half-split" it, take the FET circuit out of the mix.
Get out the voltmeter
[I could suggest using LEDs and resistors. Would that be opening another can of worms?]
With ALI and BHI high & BLI and AHI low, then ALO and BHO should be high out and BLO and AHO should be low.
Agreed?
(BLO and AHO -- L-O-L!)
The test results noted indicate... non-compliance.
I don't know your skill set or how you have this all laid out.
I hope you don't have all of the FET tabs mounted to a common heatsink.
It'd probably help if you placed a "map" on the table that you can refer to when you're sorting this out.
(I would've used different designators for the transistors which would reinforce the pairs' harmony and not the author's clockwise-arbitrary method.)
The "IOC" was a typo, I meant IC.
My skill set is marginal, at best. I am generally a pretty good adapter and modifier but not much good at ground-up design. My interest in all this is drivers for robotics project I have going.
I do not have the FETs on any heat sinks yet and I have them staggered so that the drains are not touching. I will heat sink them once I get the basic circuit working. I am testing with a very light weight motor, maybe 1A, so I should not have a heat problem.
I am open to your suggestion as to designators. Anything the helps and improves my knowledge base is greatly appreciated.
I am uploading a couple pictures of my breadboard, maybe that will help you.
Thanks,
Jim
The highside transistors provide alternate +V sources and the lowside transistors provide alternate paths to ground.
One way it's Q2/AHO---(a)motor(b)---Q3/BLO (Q1=off,Q4=off)
The other way it's Q1/BHO---(b)motor(a)---Q4/ALO (Q2=off,Q3=off)
covering the objectives.
I did get 4 LEDs hooked up and two light but I haven't gone any further with that yet. I haven't had time to figure out which two yet and I haven't tried ther alternate postions.
Jim
Jim
Maybe you forgot to show them?
From your data, the BLO BHO output is wrong as it's approx 9V when it ought to be 0.
PE - The IC's mnemonics leave much to be desired.
The article is almost 12 years old --
Had a big-wig used to tell us "Speed wins". He was wrong.
Slow and steady progress, accurate info, get it done right.
I have to do some fiddling then I will get back to you on progress. I think one thing I need to do it use a much bigger resistro as I think I am drawing too much power of the pin in the IC. What do you think?
What resistor where?
I'm not busting your chops, but you need to be specific.
Use insulation stripped from wires to cover resistor leads and so on.
It stands to reason that, knowing nothing else, if you get the wiring right then it should work.
[That best laid schemes o' mice and men gang aft aglee.]
Do you get/see my point about those output states vs their inputs?
I agree, it ~should~ work just dandy if the wiring is correct and the parts are the same. There are two parts that I used that are different. The zeners were not specified by part number so I chose a 15V zener adn the caps are ceramic rather than electrolytic.
If you mean the relationship bteween the inputs and outs nput, yes, I get that.
Ceramic vs electrolytic, probably doesn't make a difference in this case.
OK, so your work is cut out for you.
Take a look at the schematic attached.
I made some notes.
I used IRLZ14; like Glazner's, their gate threshold is "logic level".
I disagree with Glazner's not using commutation (suppressor, free-wheeling, et al.) diodes across the FETs. I did use them (D1, D2.)
I didn't use Glazner's zener regulators either, just pull-down resistors.
When Q2's gate voltage > threshold, it's on, its drain will be nearly at source potential (ground). Increasing V_gate past threshold will result decreasing V_DS (better conduction, bringing drain closer to ground).
Q1, the "high side driver" is configured as a source follower. The source voltage will be less than, but will "track", the gate voltage.
Q1 won't be in full conduction, so V_supply - Q1_V_source is across it (Q1 V_DS.)
So, with a 15V supply, I got 11.5V across my motor, running about 50mA (no load) and about 3V across Q1.
Oh well.
I didn't see these until tonight. I am looking at your circuit and the first question I have is how does it work WITHOUT bootstrapping? I the the gate voltage had to be at least V_gate plus the motor supply voltage, am I nuts?
Jim
According to the datasheet the FETs are diode protected internally, or do I misunderstand that too.
Jim
http://forums.parallax.com/showthread.php?132721-H-Bridge-Development