In terms of ease of use, one user of both devices has claimed that he found XMOS assembler easier than PASM. He'd written what was essentially the same graphics code using both chips.
If it was, timing-sensitive applications like high-end audio over Ethernet wouldn't work. XMOS leads the world in that area, and just made all their software and hardware designs open-source.
I've just ordered the PCBs for my W25Q quad SPI breakout board from PCB-Pool. Because they are so small (20mm x 24mm) I'll get 20 of them with their minimum board size. I should get them in about 12 days. Cost is just under €100 for the 20, say €5 ($7.33) each, if anyone wants one.
Leon: I really do not see the problem of using a 8-bit clocked port to latch the data... or did I miss something ? I mean why the fuss about XMOS chips not being able to do it... that it hasn't been done/published does not mean that it can't be done.... or not ?
Steve/Jazzed seems to think that it is very difficult to do it on other devices, hence this thread. Anyway, I'll have a go at it when I get my PCBs. It'll be interesting to compare the speeds of the two implementations.
Returning to Heater's troubles with XMOS determinism: I've been reading the relevant thread on the XMOS forum and he concluded that the XTA solves the problem, as I mentioned in a previous post.
Leon: I really do not see the problem of using a 8-bit clocked port to latch the data... or did I miss something ? I mean why the fuss of XMOS chips not being able to do it... that it hasn't been done/published do not mean that it can't be done.... or not ?
I'm sure any MCU (or CPU with GPIO) can do what I've suggested in "some form" with bit-banging.
I look forward to seeing other implementations. Until otherwise demonstrated, Propeller stands alone
Heater has shown that the XMOS way of doing things with hardware threads is identical to the Propeller and its cogs interacting with hub memory.
Hmm...sort of, not quite. Clearly if all your instructions take the same time to execute and you schedule execution, in hardware, of one instruction from each thread in turn then you have the logical equivalent of multitiple processors.
Except that assumes you always have the same number of threads being scheduled. Let's say 8. Obviously if one thread is inactive and hence skipped over in the scheduler then the 7 remaining threads are getting run faster. Poof, there goes your timing determinism.
In the case of X that is exactly what happens when you have more threads than the 4 pipeline slots in the processor. As you go to 5, 6 , 7 , 8 threads all the threads are slowing down.
K2 has quoted me above making exactly this argument on another forum.
User Name,
No flavor of heater's ZPU requires or even benefits from exact timing
True enough. The ZPU has no relation to this debate. Well, not until I have learned VHDL and implemented 8 of them on an FPGA with a HUB memory system. A ZPUProp:)
When edges and pulse durations need to be superimposable
If you are wiggling pins directly from software then you are right. Luckily X has hardware to clock data in and out of pins and achieve a 10ns timing resolution. Simultaneous events on different pins triggered from different threads is quite doable.
You still haven't said where XMOS has stated that their processors are non-deterministic
Alright I will. During a chat with David May over the new year break a year or two ago he admitted that because threads executing divide operations may stall other threads and because starting and stopping a thread may modulate the speed of the other threads then the phrase "100% deteministic" does not
really apply to the X chip as far as actual code execution is concerned.
However. If you can work within the performance offered by all 8 threads running at once and if you use the available hardware and language support to get your timing right then the X chip is 100% deterministic.
The X philosophy is that you are not counting instructions to get your timing right. After all you are writing your code in a high level language. They offer language features and hardware support to enable deterministic timing in a more rigorous way.
Thing is, with the Prop I can fire up a COG to run some new object in my program safe in the knowledge that the new objects time usage will not break anything in my original code. That is to say that the timing of my original objects is always deterministic even in the face of not knowing anything about other objects I may add to the program later.
This is not true of the X chip and it's threads.
The XTA (timing analyzer) cannot save you from that problem. If you original code needs near full horsepower adding a new thread may just break it. Conversely that new code you are adding might not be happy in your original program because you are running a thread to many and slowing it down.
Jazzed threw down the gauntlet, asking if two Quad SPI chips could be interfaced to any other MCU. I'm merely trying to show that it can be done. It seems like a valid topic for discussion to me.
It's just a consequence of the fact that the Prop and the chip that will not be mentioned are about the only examples of multi-core embedded micro controllers that there are. They are in a class of two at this time as far as I can tell. This state of affairs invites comparisons.
Too bad Leon didn't see Rayman's Flashpoint before deciding to build his own.
There was an opportunity for mutual good to come out of it if the X-blinders were not firmly installed.
I guess it's my fault for not mentioning it, but it's not my job to promote it.
Debate about XMOS deterministic ability is not really the topic of this thread.
Jazzed... do you know how much the shipping cost to Europa from the USA ? too much... and it takes a month too (But I'm happy with Rayman's Displays and breakout boards, very fine and nice work, I wish I'd bought them earlier ).
Leon... did you put one or two QuadSPI chips on that board ? Is it compatible with the connector in the XC-1 ?
I only put one chip on the board. It's similar to Rayman's board and is intended to be used on a prototyping area, as on the Propeller Proto Board and the XC-1/XC1A.
Jazzed... do you know how much the shipping cost to Europa from the USA ? too much... and it takes a month too
USPS Small Flat rate box, international priority mail 6 to 10 day delivery is < $14.00 USD.
Tiny boards (< 4 ounces) can be sent first class in an envelope < 1/4" thick for < $4.00.
Is this too much? The sending end seems fairly easy ....
You forget the delay at the toll , 3 weeks. And I payed I think 18 $. From the UK would be 2 or 3 days and 4 Euro .
Like I said: the sending end seems fairly easy. Europe has a long history of trade barriers in one form or another. I can't help that. I certainly won't be joining the EU to enjoy the benefits
I've allocated an 8-bit port to the two sets of I/O pins, to speed up the XMOS interface, but it should work OK with a Propeller. If he is happy with it I'll get some boards made.
I've allocated an 8-bit port to the two sets of I/O pins, to speed up the XMOS interface, but it should work OK with a Propeller. If he is happy with it I'll get some boards made.
Why do you have the HOLD*/D3 pins connected together? That would make an 7 bit bus.
SpinSocket-Flash has a Propeller, 64KB EEPROM, 6MHz crystal, and 2 flash chips connected on P0..7. I also have SpinSocket-Flash boards working with one Flash chip and one SRAM chip ... other combinations are possible.
I've considered making a Hydra board and PropellerProto compatible board with a 2x Flash socket design.
Propeller languages that use the flash are on the way.
Comments
http://www.xmos.com/news/18-may-2010/xmos-timing-analyzer-transforms-embedded-systems-development
In terms of ease of use, one user of both devices has claimed that he found XMOS assembler easier than PASM. He'd written what was essentially the same graphics code using both chips.
OK, I'll stop posting the countdown now.
Like how not to design a USB interface for a prototype board?
I've just ordered the PCBs for my W25Q quad SPI breakout board from PCB-Pool. Because they are so small (20mm x 24mm) I'll get 20 of them with their minimum board size. I should get them in about 12 days. Cost is just under €100 for the 20, say €5 ($7.33) each, if anyone wants one.
Returning to Heater's troubles with XMOS determinism: I've been reading the relevant thread on the XMOS forum and he concluded that the XTA solves the problem, as I mentioned in a previous post.
I'm sure any MCU (or CPU with GPIO) can do what I've suggested in "some form" with bit-banging.
I look forward to seeing other implementations. Until otherwise demonstrated, Propeller stands alone
Hmm...sort of, not quite. Clearly if all your instructions take the same time to execute and you schedule execution, in hardware, of one instruction from each thread in turn then you have the logical equivalent of multitiple processors.
Except that assumes you always have the same number of threads being scheduled. Let's say 8. Obviously if one thread is inactive and hence skipped over in the scheduler then the 7 remaining threads are getting run faster. Poof, there goes your timing determinism.
In the case of X that is exactly what happens when you have more threads than the 4 pipeline slots in the processor. As you go to 5, 6 , 7 , 8 threads all the threads are slowing down.
K2 has quoted me above making exactly this argument on another forum.
User Name,
True enough. The ZPU has no relation to this debate. Well, not until I have learned VHDL and implemented 8 of them on an FPGA with a HUB memory system. A ZPUProp:)
If you are wiggling pins directly from software then you are right. Luckily X has hardware to clock data in and out of pins and achieve a 10ns timing resolution. Simultaneous events on different pins triggered from different threads is quite doable.
Alright I will. During a chat with David May over the new year break a year or two ago he admitted that because threads executing divide operations may stall other threads and because starting and stopping a thread may modulate the speed of the other threads then the phrase "100% deteministic" does not
really apply to the X chip as far as actual code execution is concerned.
However. If you can work within the performance offered by all 8 threads running at once and if you use the available hardware and language support to get your timing right then the X chip is 100% deterministic.
The X philosophy is that you are not counting instructions to get your timing right. After all you are writing your code in a high level language. They offer language features and hardware support to enable deterministic timing in a more rigorous way.
This is not true of the X chip and it's threads.
The XTA (timing analyzer) cannot save you from that problem. If you original code needs near full horsepower adding a new thread may just break it. Conversely that new code you are adding might not be happy in your original program because you are running a thread to many and slowing it down.
I think I'll see if I can get this new forum software to just block all posts with the word XMOS in it...
Jazzed threw down the gauntlet, asking if two Quad SPI chips could be interfaced to any other MCU. I'm merely trying to show that it can be done. It seems like a valid topic for discussion to me.
Point taken.
It's just a consequence of the fact that the Prop and the chip that will not be mentioned are about the only examples of multi-core embedded micro controllers that there are. They are in a class of two at this time as far as I can tell. This state of affairs invites comparisons.
There was an opportunity for mutual good to come out of it if the X-blinders were not firmly installed.
I guess it's my fault for not mentioning it, but it's not my job to promote it.
Debate about XMOS deterministic ability is not really the topic of this thread.
I was intending to make some boards available to XMOS users, so I thought it better to design my own.
So none of those users would buy Rayman's boards?
Perhaps visiting his webpage would upset the balance of things.
Leon... did you put one or two QuadSPI chips on that board ? Is it compatible with the connector in the XC-1 ?
Tiny boards (< 4 ounces) can be sent first class in an envelope < 1/4" thick for < $4.00.
Is this too much? The sending end seems fairly easy ....
Like I said: the sending end seems fairly easy. Europe has a long history of trade barriers in one form or another. I can't help that. I certainly won't be joining the EU to enjoy the benefits
http://www.leonheller.com/images/W25Q_sch.pdf
It uses a 2x8 0.1" header.
I've allocated an 8-bit port to the two sets of I/O pins, to speed up the XMOS interface, but it should work OK with a Propeller. If he is happy with it I'll get some boards made.
Why do you have the HOLD*/D3 pins connected together? That would make an 7 bit bus.
SpinSocket-Flash has a Propeller, 64KB EEPROM, 6MHz crystal, and 2 flash chips connected on P0..7. I also have SpinSocket-Flash boards working with one Flash chip and one SRAM chip ... other combinations are possible.
I've considered making a Hydra board and PropellerProto compatible board with a 2x Flash socket design.
Propeller languages that use the flash are on the way.