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Propeller 2, 64 threads? — Parallax Forums

Propeller 2, 64 threads?

william chanwilliam chan Posts: 1,326
edited 2011-05-13 09:21 in Propeller 1
I heard some rumours that each Propeller 2 cog will be able to run 8 threads of 20MIPS each.
Is it true?
Can we utilize one thread for uart, one thread for keyboard, one thread for mouse, one thread for joystick and so forth?
Can "thread objects" be made for such purposes?

Comments

  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2011-05-12 21:32
    It's my understanding that the "threading" will be a form of cooperative multitasking with a little bit of hardware support. It will not be hyperthreading in the pure hardware sense of interleaved instruction processing. But that information is nearly a year old at this point and could have changed in the meantime.

    -Phil
  • Mike GreenMike Green Posts: 23,101
    edited 2011-05-12 21:40
    Rumours are just that. The Propeller 1 can run multiple threads, but has no hardware support for them. It's all done in software and it all has to fit in the same cog memory. If you look at the feature list for the Propeller 2, you don't see "threads" mentioned. On the other hand, the Propeller 2 will be substantially faster than the Propeller 1 and the ability to transfer more data faster between the cog and hub will make multiple threads much faster than they might be without those features. You can already utilize multiple threads on the Propeller 1. There's a 4 port serial driver that allows you to define up to 4 serial ports with possibly different features and share the potential throughput of the cog amongst them. There's also a combined keyboard and mouse driver that already exists. If what you mean is "can I use the concept of threading to combine several I/O drivers together without any regard for how they may combine", the answer is no. It doesn't work that way.
  • RossHRossH Posts: 5,519
    edited 2011-05-12 22:23
    Mike Green wrote: »
    The Propeller 1 can run multiple threads, but has no hardware support for them. It's all done in software and it all has to fit in the same cog memory.

    Yes, it's all done in software, but Catalina can run multiple C threads from Hub RAM. One of the Catalina multithreading demo programs (included below) runs 170 threads on a single cog. The limiting factor was that at 170 I start to run out of Hub RAM. Catalina could run many more threads if I didn't have to load display drivers etc.

    Ross.
       /***************************************************************************\
     *                                                                           *
     *                          Maximum Thread Demo                              *
     *                                                                           *
     * Demonstrates how many threads can executing concurrently on a single cog  *
     *                                                                           *
     *  (note that this is very dependent on the other drivers that are loaded)  *
     *                                                                           *
     \***************************************************************************/
    
    /*
     * include Catalina multi-threading:
     */
    #include <catalina_threads.h>
    
    /*
     * include some useful multi-threading utility functions:
     */
    #include <thread_utilities.h>
    
    /*
     * define how many threads we want (established by trial and error!):
     */
    #define THREAD_COUNT 170 
    
    /*
     * define the stack size each thread needs (established by trial and error!):
     */
    #define STACK_SIZE (MIN_THREAD_STACK_SIZE+4)
    
    /*
     * define a global variable that all threads will share:
     */
    static int ping;
    
    /*
     * function : this function can be executed as a thread.
     */
    int function(int me, char *not_used[]) {
    
       while (1) {
          if (ping == me) {
             // just reset ping to indicate we are still alive!
             ping = 0;
          }
          else {
             // nothing to do, so yield
             _thread_yield();
          }
       }
       return 0;
    }
    
    /*
     * main : start up to THREAD_COUNT threads, then ping each one in turn
     */
    void main() {
    
       int i = 0;
       void *thread_id;
    
       unsigned long stacks[STACK_SIZE * THREAD_COUNT];
    
       t_printf("Press a key to start\n");
       k_wait();
    
       // start instances of function until we have started THREAD_COUNT of them
       for (i = 1; i <= THREAD_COUNT; i++) {
          thread_id = _thread_start(&function, &stacks[STACK_SIZE*i], i, NULL);
          t_printf("thread %d ", i);
          if (thread_id == (void *)0) {
             t_printf(" failed to start\n");
             while (1) { };
          }
          else {
             t_printf(" started, id = %d\n", (unsigned)thread_id);
          }
       }
    
       // now loop forever, pinging each thread in turn
       while (1) {
          t_printf("\n\nPress a key to ping all threads\n");
          k_wait();
          for (i = 1; i <= THREAD_COUNT; i++) {
             // ping the thread
             ping = i;
             // wait till thread responds
             while (ping) {
                // nothing to do, so yield
                _thread_yield();
             };
             t_printf("%d ", i);
          }
       }
    }
    
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2011-05-12 22:59
    I recall Chip mentioning a TASKSW instruction, which was to be a special case of JMPRET that used a circular buffer. But I don't know whether it got incorporated into the final design. In any event, the task switching would have to be cooperative, not automatic.

    -Phil
  • LeonLeon Posts: 7,620
    edited 2011-05-13 02:00
    I heard some rumours that each Propeller 2 cog will be able to run 8 threads of 20MIPS each.
    Is it true?
    Can we utilize one thread for uart, one thread for keyboard, one thread for mouse, one thread for joystick and so forth?
    Can "thread objects" be made for such purposes?

    That's how threads are used on XMOS devices. They usually support one peripheral function, like Propeller cogs, but that isn't necessarily the case.
  • RossHRossH Posts: 5,519
    edited 2011-05-13 02:18
    Leon wrote: »
    That's how threads are used on XMOS devices. They usually support one peripheral function, like Propeller cogs, but that isn't necessarily the case.
    *groan!*
  • LeonLeon Posts: 7,620
    edited 2011-05-13 02:57
    Parallax probably filched the hardware thread concept from XMOS. :)

    XMOS has a large number of patents on their technology, Parallax needs to check for any infringement.
  • RossHRossH Posts: 5,519
    edited 2011-05-13 03:26
    Leon wrote: »
    Parallax probably filched the hardware thread concept from XMOS. :)

    XMOS has a large number of patents on their technology, Parallax needs to check for any infringement.

    Leon, you are a loon!

    XMOS has a patent on multithreading? Give me a break!

    Ross
  • LeonLeon Posts: 7,620
    edited 2011-05-13 03:35
    They could have a patent on how how they have implemented it!

    I didn't just mean hardware threading, anyway; there might be other items. With all the patent litigation going on at present, it pays to be careful.
  • Heater.Heater. Posts: 21,230
    edited 2011-05-13 03:46
    RossH,
    XMOS has a patent on multithreading? Give me a break!

    I am sure they have not.

    You can find the three patents belonging to XMOS here http://www.patentbuddy.com/Company/Profile/XMLCITIES-INC/207399

    They are all hardware related. I don't much like how the patent system is going and I hate the idea of software patents the most. I think I can tolerate these patents though.
    One of them is to do with compact instruction set decoding.
    Two of them are to do with the tight integration at the hardware level between the I/O ports on a system and the hardware thread scheduling in the CPU.

    Not at all bad.

    David May has a bunch of other patents as a result of his long research career, no idea if they are relevant or not.

    This poses a bit of a paradox. XMOS has a catch phrase "software defined silicon" which encapsulates the idea that any logical function you care to perform can be done in hardware with a bunch of gates or in software on a CPU. Given enough speed.

    Ergo, any patent on the description of a digital circuit is equivalent to a patent on a software algorithm. Which can be shown to be the equivalent of a piece of mathematics.
    Mathematics is not patentable. In many places software is not patentable.

    Ergo, digital logic designs and concepts should not be patentable either.
  • RossHRossH Posts: 5,519
    edited 2011-05-13 03:59
    Heater. wrote: »
    RossH,



    I am sure they have not.

    You can find the three patents belonging to XMOS here http://www.patentbuddy.com/Company/Profile/XMLCITIES-INC/207399

    They are all hardware related. I don't much like how the patent system is going and I hate the idea of software patents the most. I think I can tolerate these patents though.
    One of them is to do with compact instruction set decoding.
    Two of them are to do with the tight integration at the hardware level between the I/O ports on a system and the hardware thread scheduling in the CPU.

    Not at all bad.

    David May has a bunch of other patents as a result of his long research career, no idea if they are relevant or not.

    This poses a bit of a paradox. XMOS has a catch phrase "software defined silicon" which encapsulates the idea that any logical function you care to perform can be done in hardware with a bunch of gates or in software on a CPU. Given enough speed.

    Ergo, any patent on the description of a digital circuit is equivalent to a patent on a software algorithm. Which can be shown to be the equivalent of a piece of mathematics.
    Mathematics is not patentable. In many places software is not patentable.

    Ergo, digital logic designs and concepts should not be patentable either.

    Heater,

    We both know (as should anyone who has ever dealt with patents) that holding a patent is one thing. Being able to enforce it is quite another.

    Anyone who thinks XMOS can enforce a patent on multithreading is a loon!

    Ross.
  • LeonLeon Posts: 7,620
    edited 2011-05-13 04:14
    I didn't say that! I said that their hardware threading technique might be patented. As Heater pointed out, there is a patent associated with it.
  • RossHRossH Posts: 5,519
    edited 2011-05-13 04:47
    Leon wrote: »
    I didn't say that! I said that their hardware threading technique might be patented. As Heater pointed out, there is a patent associated with it.

    Leon, I don't care what anyone says - you are an endless source of amusement!

    Ross.
  • LeonLeon Posts: 7,620
    edited 2011-05-13 04:52
    I do my best. :)
  • Heater.Heater. Posts: 21,230
    edited 2011-05-13 05:15
    RossH,
    ...holding a patent is one thing. Being able to enforce it is quite another.

    Indeed, it helps to have big piles of money and lawyers. That's one of the crazy things about the patent as intellectual property idea. In the world of real property, say my garden or my car, the law says it's mine and the law might even offer me some protection from trespassers, thieves etc etc. Not so with IP where there is no protection for the little guy.
    Anyone who thinks XMOS can enforce a patent on multithreading is a loon!

    I don't know, RAMBUS and such have managed to do such things. XMOS has some money and lawyers I'm sure.
  • LeonLeon Posts: 7,620
    edited 2011-05-13 05:22
    Anyway, hardware threads aren't mentioned in the current specification, so the idea has probably been dropped.
  • pjvpjv Posts: 1,903
    edited 2011-05-13 09:21
    Hello William;

    An interesting discussion indeed.

    Presently, on the Prop1, we can already run 144 simultaneous assembler threads of a trivial nature in each cog .... flashing LEDs. So a total of 1132 threads.... a totally useless exercise with 32 I/O pins.

    For real work, the number is a more practical 6 to 8 threads per cog, depending on each thread's needs. Afterall, the cog has a finite amount of processing power. And those would run at full speed when active, with a timing granularity of 1 uSec, and a task switch time just under one uSec. The threads are relatively independent of each other from a timing perspective, but totally code independent of each other. However, they do need to be written in a co-operative manner to interface with a tiny software Scheduler kernel.

    With the Prop2's pipeline architecture and higher speed, as well as whatever new clever instructions, it should be quite a spectacle. Seriously looking forward to that.

    Cheers,

    Peter (pjv)
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