Low cost custom Poly IC Design?

davidsaunders

I have a friend that has the needed ION guns, wafers, etc to make very low density ICs (no clean room). He has demonstrated the ability to make simple devices with a 70% success rate.
The limit of his process is about 100Micrometer (due to the constraints of not having a clean room).

My question is:
What would be the practical limits of size for a VLSI device this way?
What is the largest die that could be reasonably used?
What would be the fastest transistor implementation in this technology?
Presuming Junction as the answer to the last; What would be the fastest FET transistor implementation?
Where can I find more information on the limits of working at 100Micrometer for VLSI IC production?

Beau Schwabe

Just to help put it in perspective...

- There are 25400 microns in one inch

- A large die is considered to be anything over 10mm square or ( about 0.4 inches square )

- So at 0.4 inches you have about 10160 microns a side

- If your friends process limits him to 100 microns that's 101 transistors realistically about 1/3rd of that (<-- you need routing room to connect to the source drain and gate) .... So 33 transistors a side

- At 33 transistors a side yo might expect a density of 1089 transistors for the entire die.



As a side note: At a 100um resolution, You might be able to implement a printing process to deposit the layers. A single dot from a 300 dpi printer is just under 85 microns in diameter.

davidsaunders

At a 100um resolution, You might be able to implement a printing process to deposit the layers. A single dot from a 300 dpi printer is just under 85 microns in diameter.

Thank you for this suggestion. I will look into this possibility.

I am still interested to find out what the limit is for switching speed for FETs at this size?

Beau Schwabe

"I am still interested to find out what the limit is for switching speed for FETs at this size" - Without imperical testing to characterize the transistors it would be almost impossible to tell. There are several factors depending on the 'recipe' used to place the transistors. Even if a transistor has the same square area as another, the aspect ratio can make an impact on speed. Just too many variables unless you can define a particular series of steps for the process itself that can be repeatable, and then characterize the results by running a test chip. Typically components are created in powers of two ( X1, X2, X4, X8, X16, etc. devices) and characterized by how they respond.... to gate voltage, capacitance, etc.

See the BLOG I posted here.... http://forums.parallax.com/entry.php?189-What-does-an-IC-Layout-Engineer-do-exactly-in-layman-s-terms

davidsaunders

Thank you. To make some test dies it is.