I have been saying for a while that 3D is the way to improve chip performance.
Not that it was my idea, I just concurred with it the first time I heard it discussed
at a conference. The trick will be layering multiple processors vertically while
managing to somehow keep the stack from melting due to the heat. Tiny pores
and channels where some type of fluid could be circulated might be the way to
do it. Of course it would take so many interconnections to transfer data in something
like a 3D stack of processors that optical data handling would be needed.
Some day a small 3D CPU cube that is the equivalent of a super computer today will
sit on a circuit board and have only power pins and optical data connections.
I'm not sure what the reject rate would be for something like that though!?
1000+ cores in a single device would be very lucky to not have a single error.
Perhaps the ability to permanently route around bad cores would be the only
way to proceed.
If you look at the description carefully, it's not that big of a deal. In terms of memory cells and discrete MOSFETs, people have been building and using 3D structures for some time. Power MOSFETs have used 3D construction for years. It looks here like there's an incremental increase in fine detail and deposition of different layers on vertical structures than has been done before, a nice improvement in circuit density.
Technically it's a 3-d process right now, just not very high ... it's a matter of perspective. What you have to worry about when building upwards is planarization and routability.
As far as stacking die, another 3-d trick, the chip yield usually goes way down because of stress during the processing. Essentially it works like BGA (Ball Grid Array) but at the silicon level. Personally I have designed a few chips like this and they are a pain... you end up loosing a lot of silicon real estate just for the 'keep out' region that the connections need to be located at.
There is also the cost ... many new methods are cost prohibitive until the process matures. Manufacturers like to stick to known recipes that work and that are well characterized unless the manufacturer is on the forefront of developing the new process to begin with. In that case they usually have the investments to back their R&D efforts.
Comments
I have been saying for a while that 3D is the way to improve chip performance.
Not that it was my idea, I just concurred with it the first time I heard it discussed
at a conference. The trick will be layering multiple processors vertically while
managing to somehow keep the stack from melting due to the heat. Tiny pores
and channels where some type of fluid could be circulated might be the way to
do it. Of course it would take so many interconnections to transfer data in something
like a 3D stack of processors that optical data handling would be needed.
Some day a small 3D CPU cube that is the equivalent of a super computer today will
sit on a circuit board and have only power pins and optical data connections.
I'm not sure what the reject rate would be for something like that though!?
1000+ cores in a single device would be very lucky to not have a single error.
Perhaps the ability to permanently route around bad cores would be the only
way to proceed.
http://www.xilinx.com/technology/roadmap/ssi-technology.htm
It might offer greater densities than Intel's technique.
As far as stacking die, another 3-d trick, the chip yield usually goes way down because of stress during the processing. Essentially it works like BGA (Ball Grid Array) but at the silicon level. Personally I have designed a few chips like this and they are a pain... you end up loosing a lot of silicon real estate just for the 'keep out' region that the connections need to be located at.
There is also the cost ... many new methods are cost prohibitive until the process matures. Manufacturers like to stick to known recipes that work and that are well characterized unless the manufacturer is on the forefront of developing the new process to begin with. In that case they usually have the investments to back their R&D efforts.