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Attention C3 owners: VGA test request — Parallax Forums

Attention C3 owners: VGA test request

kuronekokuroneko Posts: 3,623
edited 2011-04-19 18:17 in Propeller 1
The attached archive contains a simple 64 column VGA text driver demo. This is in effect the same demo Bill is using for his drivers with the additional VGA buffer enablement for the C3.

So if you have a minute could you please run this demo and report success/failure? Thanks.

It's also usable on the demoboard.
zip
zip
MikronautsVGA64_demo - Archive [Date 2011.04.18 Time 10.56].zip
10K

Comments

  • localrogerlocalroger Posts: 3,452
    edited 2011-04-17 19:24
    Will be happy to run this, but won't be back to work where my C3 is until Tuesday. Will test & post then if it's not resolved.
  • Bill HenningBill Henning Posts: 6,445
    edited 2011-04-18 19:16
    I was able to steal a few minutes minutes from UPEW preparations to fire up the C3 Ken was kind enough to send to me...

    My 64 and 50 column drivers work just fine, once you enable VGA output on the C3 :-)

    In my demo's start method, add the following lines so it looks like this:
    PUB start

  ' if running on a C3, un-comment the two lines below
  dira[15]~~   ' set P15 to output
  outa[15]~    ' pull P15 low to enable VGA output
  ' end of C3 fix

  vga.start(16)

    Both drivers run perfecly on my little 5" VGA OEM module, every time.

    Now when I can steal some more time, I just have to get the 80 column driver running with kuroneko's hub/waitvid sync lock patch...
  • RossHRossH Posts: 5,519
    edited 2011-04-19 03:19
    Hi Kuroneko (& Bill!),

    Your demo runs fine on my C3. I tried a few different modes and everything seems to work ok - and my LCD monitor is a wee bit choosy! - well done.

    Ross.
  • Bill HenningBill Henning Posts: 6,445
    edited 2011-04-19 06:04
    Glad to hear it works well for you!

    kuroneko's patch for forcing the video output to synchronize with the hub fixed the "I will only sync when I feel like it" issue; which was caused by some pipelining weirdness.

    I also have a single cog 40 column VGA text driver; once I patch that, I will also release that driver.
  • RsadeikaRsadeika Posts: 3,837
    edited 2011-04-19 06:15
    I do not know how everybody else is testing, but for me it usually starts out fine, then after the fifth or sixth reload to RAM it would clunk out. The last one that I did it took ten or eleven reload to RAM before it clunked out. Where are the latest driver(s) at, or I can assume that the driver(s) did not change?

    Ray
  • kuronekokuroneko Posts: 3,623
    edited 2011-04-19 06:37
    Rsadeika wrote: »
    I do not know how everybody else is testing ...
    Just for you (right now) I uploaded the demo from the top post 50 times to RAM (demoboard). Worked 50 out of 50 times (64 columns, 5MHz/PLL16x). I also forced different cogs (not just #1) because I know they have different startup behaviour. Same result.
  • kuronekokuroneko Posts: 3,623
    edited 2011-04-19 06:51
    Bill Henning wrote: »
    ... which was caused by some pipelining weirdness.
    You make it sound worse than it is. And most importantly, you forgot to blame the PLL :)
  • trodosstrodoss Posts: 577
    edited 2011-04-19 07:11
    kuroneko,
    It works fine for me on the C3 hardware (loaded it 20 times).
  • Bill HenningBill Henning Posts: 6,445
    edited 2011-04-19 08:12
    Bad PLL! Bad, Bad, Bad!
    kuroneko wrote: »
    You make it sound worse than it is. And most importantly, you forgot to blame the PLL :)
  • KMyersKMyers Posts: 433
    edited 2011-04-19 11:01
    Works fine also on my C3....
  • CogSaverCogSaver Posts: 17
    edited 2011-04-19 12:11
    Works every time on my C3 as well,

    Could someone please point me towards the explanation of the magic that takes place when 
    cmp     color,pixel
    apparantly takes the place of a 
    waitvid color,pixel
  • kuronekokuroneko Posts: 3,623
    edited 2011-04-19 18:17
    Thanks to everyone reporting their results. I really just needed a second opinion on this and apparently it now also works for the person reporting the issue although it's not entirely clear why. The only change is a slightly shuffled startup sequence (C3 VGA enable, VGA driver start). If anyone feels like investigating the issue see [post=993213]this post[/post].
    CogSaver wrote: »
    Could someone please point me towards the explanation of the magic that takes place when 
    cmp     color,pixel
    apparantly takes the place of a 
    waitvid color,pixel
    I don't have anything to point you at (except suggesting a tag search for waitvid and reading the relevant thread(s)).

    That said, initially all instructions go through the same steps which is fetching src and dst. waitvid isn't different, its primary function is add and it has some h/w attached to sync with the video circuitry. IOW, all it does is latch the data, wait and then add (nr style). The only real difference to add is the ability to wait for the (waitvid) hand-off point (WHOP). Now, if we know when the WHOP happens then there is no point waiting, we just make sure the data is latched and go about our business.

    In the case of Bill's VGA driver this is what we do, i.e. arrange it so that the WHOP is located conveniently about 4 cycles after a rdlong which gives the cmp (or any other suitable instruction, e.g. ones color, pixel nrA) enough time to latch dst (colour) and src (pixel) info and then we still have enough cycles left for an embedded djnz.


    A we need dst intact for each line
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