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1Mbit EEPROM — Parallax Forums

1Mbit EEPROM

EMPTY_CEMPTY_C Posts: 29
edited 2011-03-31 09:07 in BASIC Stamp
Hello All,

I am creating a data logger using microchip's 24LC1025 EEPROM; in order to do this I was adapting a code from the stamp works book:

SW21-EX32.BS2

I changed the read/write location : wrdAddr to show 0 to 65535 to indicate all the possible addresses (2^16) or did I?

I have a feeling that there are more addresses to write to; according to the documentation: "the device has an internal addressing boundary limitation that is divided into 2 segments of 512K bits."

At this time I am assuming that I am operating in one 512K bit block of memory.

My question is: What is my address range? (assuming I am writing to a 512K bit block of memory)

Thank you for your help!

MT
BS2
BS2
SW21-EX32.BS2
6K

Comments

  • vaclav_salvaclav_sal Posts: 451
    edited 2011-03-30 19:42
    Consult / read thei specification http://ww1.microchip.com/downloads/en/DeviceDoc/21941G.pdf
    Pay attention to hardware requirement on Ax pins, especially A2.

    As far as addressing / capacity.
    The physical address is 16 bits word ( same as in your code sample) plust the additional two bits A0 A1 in control word.
    Per spec , the device physical capacity is 128K x 8 and you can control four of them (4x 128 Kbits ) on the same address bus.

    The "block" feature is generaly used when consecutive read / write ( not sure about write) is required.
    I need to do some "digesting" spec desription of block. I am not sure how they came up with two 512K "parts".

    Cheers Vaclav
  • Mike GreenMike Green Posts: 23,101
    edited 2011-03-30 20:29
    This EEPROM looks like two 64K byte EEPROMs. The 24LC1025 looks like there's one 64K area at device address %0XX and the other at %1XX where XX is A1/A0. The 24LC1025B changes this so the two blocks are adjacent at %XX0 and %XX1 which is compatible with what other manufacturers do.
  • vaclav_salvaclav_sal Posts: 451
    edited 2011-03-30 20:50
    Mike, your explantion makes sense, but where did the "512K' in the spec came from?
    And similar text is in there twice.


    "Each device has internal addressing boundary
    limitations. This divides each part into two segments of
    512K bits. The block select bit ‘B0’ controls access to
    each “half”."

    Vaclav
  • EMPTY_CEMPTY_C Posts: 29
    edited 2011-03-31 02:46
    vaclav_sal wrote: »
    Consult / read thei specification http://ww1.microchip.com/downloads/en/DeviceDoc/21941G.pdf
    Pay attention to hardware requirement on Ax pins, especially A2.

    I do have A2 set to 1.
    vaclav_sal wrote: »
    As far as addressing / capacity.
    The physical address is 16 bits word ( same as in your code sample) plust the additional two bits A0 A1 in control word.

    I have A0 and A1 set to 0,0 respectively. If I wanted to add more capacity I could add up to 3 more chips and make their A0,A1 to: 1,0 ; 0,1; 1,1. This would give my system a total of 4 Mbits.
    vaclav_sal wrote: »
    Per spec , the device physical capacity is 128K x 8 and you can control four of them (4x 128 Kbits ) on the same address bus.

    I am not sure if I agree with the above quote. I thought for a given address, say 0,0 (A0,A1) and setting the block select bit to 0 that I would have a capacity of 512 Kbits.

    Thanks for your help

    MT
  • EMPTY_CEMPTY_C Posts: 29
    edited 2011-03-31 02:50
    Mike Green wrote: »
    This EEPROM looks like two 64K byte EEPROMs. The 24LC1025 looks like there's one 64K area at device address %0XX and the other at %1XX where XX is A1/A0. The 24LC1025B changes this so the two blocks are adjacent at %XX0 and %XX1 which is compatible with what other manufacturers do.

    So does this mean that I have 64000 addresses to write to on %0XX and 64000 addresses on %1XX totaling 128000 addresses?

    According to the documentation I should have an address boundary of 0000h (0) to FFFFh (65535) (within %0XX). This seems a little confusing to me.
  • vaclav_salvaclav_sal Posts: 451
    edited 2011-03-31 06:52
    Yep, as Mike said - there are two 64K memories in the device - "blocks".
    There must be an error in the spec when they talk about anything "512K".- it should be "64K".
    Do not forget to add the device ID to the control word.
    Vaclav
  • UnsoundcodeUnsoundcode Posts: 1,532
    edited 2011-03-31 07:40
    Hi, EEPROMs are specc'd by number of bits, The EEPROM in question is 1M bits (1024K bits) which works out to two equal blocks 512K bits (divided by 8 = 64K bytes for each block). A kilobyte is 1024 bytes so 1024 X 64 = 65536 bytes of addressable memory for each block ( $0000 to $FFFF ). To address the first block the block select bit B0 should be at logic zero and for the second block the block select should be at logic one.

    Jeff T.
  • vaclav_salvaclav_sal Posts: 451
    edited 2011-03-31 09:07
    Never too old to learn!
    This just shows how important is to pay attention to “details”.
    I did not and overlooked the bits versus bytes!
    The spec is correct when it talks about 512 kbits “blocks”.
    Vaclav
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