SPI interface wants 40-60% clock duty cycle

retasker

I am trying to interface a BS2 to a MAX1030 16 channel ADC. I am not sure at this point that it does not work, but the datasheet says that it requires a 40-60% clock duty cycle. The SHIFTOUT command does not result in a duty cycle within this range (more like 25%).

I need to send data to the ADC to set it up and to start a conversion cycle. I will certainly see if it will work even though the clock duty cycle is out of spec for their requirements, but...

Is there any way to generate the data and clock streams where the clock is within the required range of duty cycle?

Dick Tasker

Phil Pilgrim (PhiPi)

Because the datasheet specifies a minimum clock period, rather than minimum clock highs and lows, my guess is that the 40-60% duty cycle range applies only at maximum clock speeds, not for the slower rates at which the BS2 will be clocking data. The datasheet doesn't say so explicitly, but that's my take on the spec.

-Phil

retasker

I hadn't thought of it that way, but you may very well be right as this is supposed to work up to 4.8MHz for conversion and up to 10MHz for data I/O. I will continue tomorrow evening and see what happens. Thanks for the comment.

Dick Tasker

sam_sam_sam

When you get a working code can you please post it I would like to get an Idea how to use this chip my self

Thanks