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When to use SRAM, SD Card, SPI flash, and EEPROM? — Parallax Forums

When to use SRAM, SD Card, SPI flash, and EEPROM?

groggorygroggory Posts: 205
edited 2011-02-10 09:33 in Propeller 1
Ok, here are my ideas on the three major types of external data storage that we use on this platform. Please chime in and tell me when it's right...

SRAM - When you essentially need more HUB memory add SRAM. Alternatively, if you have large pre-compiled programs that would not otherwise be loadable, load them into SRAM. So let's say I wanted to make a GIANT array of longs and wanted to be able to access that array from any of my cogs. The HUB memory would be a great use for this as long as it were enough. If it weren't enough then SRAM would be a great way to make this happen. Of course, you could potentially treat SRAM as external RAM dedicated to a cog ... but it is really accessible through any of the cogs. :-/ Please fill me in more on how this works. I've never used SRAM but am trying to wrap my head around how to use it. It is addressable by memory address pointers. Price - $1.62 / 256 kbit

SD Card - You cannot access this directly by memory address pointers. You need to use some sort of file system for this. Most people who use the SD card are using a version of the FAT16 file system. This is relatively fast, can write to one file at a time (but can have multiple 'open' files). You can read files from this directly on a windows computer. SD drive is a bit heavy because there is a fair amount of overhead to access and write to it. Price - $5/ 2GB + $4/ Socket

SPI Flash - Has an onboard memory controller so you can treat it like SRAM. Takes numerous clock cycles to read and write to (unlike SRAM), but for all intents and purposes can be used in lieu of SRAM...it just isn't as fast. What you lose in speed you make up for in storage per dollar. It is easy to use, inexpensive, and relatively large.
Price - $1.12/ 4 megabyte

EEPROM - This is what the propeller expects to pull from in terms of booting. You can only read from one page of memory at a time, so for large storage applications EEPROMs are a pain in the butt. Also, you can only write to them so many times before they start wearing out. They are not good for repeated mass storage, but they are good for storing of variables or settings at boot-time. Inexpensive but useful. It seems to me that if you are planning to use FLASH memory that an additional 'storage' EEPROM would just be frivilous. Price 512kbyte/$1.28 or 1megabyte/ $2.88

Comments

  • jazzedjazzed Posts: 11,803
    edited 2011-02-08 14:19
    HUB memory can not be simply extended by adding an SRAM chip; however, there are solutions that allow adding usable external memory.

    Catalina C supports several board types and is functional.
    Zog C supports C3 and SDRAM and is functional.
    BigSpin targets different hardware, but it is in early prototype stage with SDRAM, and others.
    PropellerJVM can run Javelin programs stored in EEPROM.
    There are others ....
  • Bill HenningBill Henning Posts: 6,445
    edited 2011-02-08 14:25
    groggory wrote: »
    Ok, here are my ideas on the three major types of external data storage that we use on this platform. Please chime in and tell me when it's right...

    SRAM - When you essentially need more HUB memory add SRAM. Alternatively, if you have large pre-compiled programs that would not otherwise be loadable, load them into SRAM. So let's say I wanted to make a GIANT array of longs and wanted to be able to access that array from any of my cogs. The HUB memory would be a great use for this as long as it were enough. If it weren't enough then SRAM would be a great way to make this happen. Of course, you could potentially treat SRAM as external RAM dedicated to a cog ... but it is really accessible through any of the cogs. :-/ Please fill me in more on how this works. I've never used SRAM but am trying to wrap my head around how to use it. It is addressable by memory address pointers. Price - $1.62 / 256 kbit

    There is no external memory that is directly addressable; all external memory uses I/O to communicate with the Prop.

    SPI memory normally uses 4 prop pins, and the address has to be shifted out serially.

    Parallel ram needs the address supplied however it is implemented.

    Prices vary depending on type/size of memory, it is not as simple as $1.62/256kbits (32KB)
    groggory wrote: »
    SD Card - You cannot access this directly by memory address pointers. You need to use some sort of file system for this. Most people who use the SD card are using a version of the FAT16 file system. This is relatively fast, can write to one file at a time (but can have multiple 'open' files). You can read files from this directly on a windows computer. SD drive is a bit heavy because there is a fair amount of overhead to access and write to it. Price - $5/ 2GB + $4/ Socket

    You can address it 512 byte block at a time, you do not need a file system. Prices vary.
    groggory wrote: »
    SPI Flash - Has an onboard memory controller so you can treat it like SRAM. Takes numerous clock cycles to read and write to (unlike SRAM), but for all intents and purposes can be used in lieu of SRAM...it just isn't as fast. What you lose in speed you make up for in storage per dollar. It is easy to use, inexpensive, and relatively large.
    Price - $1.12/ 4 megabyte

    Just as fast for read as SPI ram, slower for write.

    There is a limit on how many times a sector can be erased.

    Prices vary. SD cards are much cheaper, and take care of "wear levelling" for you.
    groggory wrote: »
    EEPROM - This is what the propeller expects to pull from in terms of booting. You can only read from one page of memory at a time, so for large storage applications EEPROMs are a pain in the butt. Also, you can only write to them so many times before they start wearing out. They are not good for repeated mass storage, but they are good for storing of variables or settings at boot-time. Inexpensive but useful. It seems to me that if you are planning to use FLASH memory that an additional 'storage' EEPROM would just be frivilous. Price 512kbyte/$1.28 or 1megabyte/ $2.88

    One EEPROM is needed to boot.

    Takes approx. 10x longer to wear out than FLASH.

    I2C version is MUCH slower for reads than ram or flash.
  • MagIO2MagIO2 Posts: 2,243
    edited 2011-02-08 15:24
    2 cents about SD card:
    "You need to use some sort of file system for this" - this is not true. It's only desirable to use FAT16 or 32 because then you can simply put the card into an SD card reader and copy stuff from and to the card with a PC. If you don't need that, you can live without a filesystem.
    I wrote some addon functions for FSRW which access one big file by simple address pointers inside of the file. So, it's a mixture - it is a regular FAT file, but when accessing it the functions no longer care about FAT. It simply reads/writes in 512 byte sectors. By the way the functions support up to 4 files (full access) plus the original FSRW functions can deal with an open file at the same time.
  • Dr_AculaDr_Acula Posts: 5,484
    edited 2011-02-08 15:50
    re
    flash...but for all intents and purposes can be used in lieu of SRAM

    Not quite. Flash ram wears out as it has a limited number of writes. EEPROM and SD memory also wears out.
    SRAM never wears out.

    But SRAM loses its memory when you power off. Flash/SD/EEPROM keep their memory when powered off.

    Choose the one that fits your application.

    SRAM - serial is like you say, $1.62 per 256kilobit. You could also use parallel SRAM - faster and price is about $3 for 4 megabits.
    Of course, you could potentially treat SRAM as external RAM dedicated to a cog ... but it is really accessible through any of the cogs. :-/ Please fill me in more on how this works.

    That is an intriguing idea. You could put an sram driver in a cog and that would use a certain percentage of the cogs memory. Maybe 10 to 20%?
    You could also have a dedicated cog doing external sram access, and talk to that cog from other cogs via hub ram. Request a byte from this address etc.
    I don't think either of these have been coded but they could be. They only increase data storage space though, not code space.

    The third option does increase code space and data spacefor a cog, and is called LMM. This allows huge Pasm programs, hundreds of kilobytes long, but it is slower than standard cog speeds. If you want to know more about this please let us know.
  • localrogerlocalroger Posts: 3,452
    edited 2011-02-08 15:54
    To add a few cents of my own:

    There is no cheap universal solution for adding SRAM. There are many solutions out there offering different compromises, some of which are supported by alternate development environments but none of which are as fast or versatile as Hub RAM.

    SPI RAM is fast and lasts forever but is only available in relatively small packages; at 32K per 8-pin DIP you're not expanding by much and you quickly end up having to do something creative to herd CS pins. Bill Henning (who already posted) has a product called FlexMem which is pretty neat, using 4 SPI RAM chips to get 4 times the throughput with a reasonable number of pins.

    As others have noted you don't have to use a file system for SD card. In fact, you don't even need one to offload data to a PC; just preformat the card with a large contiguous file, and all you have to tell the Prop is what sector its data starts at. It's very cheap, but does have that block oriented 512 byte at a time thing going. It you start churning blocks it can get very time consuming to access SD.

    Don't use SPI flash. Just don't.

    EEPROM lasts longer than flash when churned and can be accessed a byte at a time. In some applications this can make up for a lot of the difference between 1 MHz I2C and the 20 MHz SPI speeds. Since the Prop needs EEPROM anyway you can often get 96K for free just by changing out the 32K chip a board came with with a 128K chip. And you can go all the way to 512K without using any more pins. EE does wear out but it takes about a million operations to wear out a bit compared to 10,000 for flash, and you can access it in much smaller blocks than any form of flash so it's not too hard to manage that.

    Large EEPROMs have 128 byte pages and it's not too hard to code a driver to automatically re-address when "next byte please" crosses a page boundary.
  • Cluso99Cluso99 Posts: 18,069
    edited 2011-02-08 16:01
    As magio2 said: You can directly address the SD card using the low level drivers. Just give it a sector address and you can read and write to it. For an example, see ZiCOg (the Z80 CPM emulator). We use a contiguous file under FAT16. If the SD card is formatted and a fixed length file is created (copy a blank file from the PC - IIRC there are 32MB files I created in the ZiCog thread). ZiCog locates the file under FAT16 and takes that address as the base and you access the file relatively (directly) from there.

    Originally heater used the SD card directly with no FAT16. You maybe able to find his original code in the thread.

    As for SRAM, any cog can access it so you will have to ensure that more than 1 cog does not try this. It is fast but you waste I/O pins for the address. For instance, my RamBlade uses 512KB so 19 pins are address, 8 pins data, 2 pins for control (varies CE, WE, OE depending on config). I then use another pin for CS control of the microSD, which shares the 3 spi pins with the data pins. That leaves 2 pins for communications with another prop. You cannot access both SD and SRAM simultaneously as they share pins.

    Your SD socket is overpriced. Try Digikey HR1941CT-ND for an easy to solder by hand smt microSD socket.
  • jazzedjazzed Posts: 11,803
    edited 2011-02-08 16:04
    Dr_Acula wrote: »
    SRAM - serial is like you say, $162 per 256kilobit. You could also use parallel SRAM - faster and price is about $3 for 4 megabits.
    On that scale SDRAM is essentially free :)
  • Mike GreenMike Green Posts: 23,101
    edited 2011-02-08 16:04
    There's an SPI Flash memory driver (in the ObEx) for Winbond Flash memories that provides a simple file system and supports SPI SRAM as well. The file system allows for sequential writing of named files and both sequential and random reading of files. There's a very simple "wear levelling" provision that uses the file name and 4K block number to generate the first location to look for an available block for writing.
  • David BetzDavid Betz Posts: 14,516
    edited 2011-02-08 16:22
    localroger wrote: »
    Don't use SPI flash. Just don't.
    Care to explain that comment? :-)
    I use the SPI flash on the C3 to hold ZOG code and the SPI SRAM to hold the data. This lets me run programs with up to 1mb of code and 64k of data. I don't attempt to put volatile data in flash so I don't expect to have much trouble with wearing out the flash chip. Is that what you are worried about?
  • localrogerlocalroger Posts: 3,452
    edited 2011-02-09 13:29
    I've seen people wear out EEPROMs in RL applications. The temptation to use them for often changing data can be very strong, and it can be hard to work out a wear reducing scheme that doesn't hammer some index location. If you're using the chip for development, and you have to recompile your work between iterations, I could easily see wearing out a SPI flash in the course of a project. And memory wear-out is the kind of thing that will sneak up behind you and waste days of your time trying to figure out what's going wrong when it happens. I just wouldn't use un wear-leveled flash unless I had a very, very good reason.
  • LeonLeon Posts: 7,620
    edited 2011-02-09 13:55
    Flash memory has been used for years to store microprocessor and DSP programs, and to load FPGAs, without any problems. In many cases, it isn't actually used during development, so read-write cycles aren't relevant.
  • David BetzDavid Betz Posts: 14,516
    edited 2011-02-09 15:17
    localroger wrote: »
    I've seen people wear out EEPROMs in RL applications. The temptation to use them for often changing data can be very strong, and it can be hard to work out a wear reducing scheme that doesn't hammer some index location. If you're using the chip for development, and you have to recompile your work between iterations, I could easily see wearing out a SPI flash in the course of a project. And memory wear-out is the kind of thing that will sneak up behind you and waste days of your time trying to figure out what's going wrong when it happens. I just wouldn't use un wear-leveled flash unless I had a very, very good reason.
    The SPI flash chip on the C3 is good for 100k erase cycles. I think you'd have to do a tremendous amount of edit download cycles to ever reach that number. 100/day for three years straight would do it I guess. :-)
  • Dr_AculaDr_Acula Posts: 5,484
    edited 2011-02-09 15:56
    @jazzed
    On that scale SDRAM is essentially free
    - yikes! I left out a decimal point. D'Oh. Ok, I changed $162 to $1.62.

    Even so, $/byte, parallel ram works out cheaper than serial ram, even when you add the overhead of support chips. (To our original poster, jazzed has a design with 32megabytes of sram)

    Re using SPI ram, @David, that is an interesting model using the flash for code and the hub for data. I pondered this recently when looking at a netbook computer running windows. How do they stop all the hard disk thrashing, because since about windows 3.1 there has been a temporary disk file that has been used to emulate the memory (that was going to be cheaper a few years later but wasn't at that point). Either they have rewritten windows, or maybe the netbook is designed to wear out? The perfect inbuilt obsolescence?

    Do you have zog code that has been designed to separate code and data memory? (because I'm not sure Spin or C or Basic can do this)

    Re localroger
    Don't use SPI flash. Just don't.
    I tend to agree with that. $/byte, I think SD works out a lot cheaper than Flash memory. Plus, if ever a card wears out you can replace it. Plus the wear levelling is done internally. Plus, once you get over about a megabyte, it is much quicker to pop out an sd card and put it in a USB reader than it is to download data via a serial port.
  • jazzedjazzed Posts: 11,803
    edited 2011-02-09 16:05
    Leon wrote: »
    In many cases, it (flash) isn't actually used during development, so read-write cycles aren't relevant.
    I guess I never worked for the right company ;-)

    Dr_Acula wrote: »
    @jazzed - yikes! I left out a decimal point. D'Oh. Ok, I changed $162 to $1.62.
    SDRAM is essentially free on that scale too.

    ZOG can use Flash and SRAM or just SRAM (both with SD Card support) - Good work David Betz!.
  • David BetzDavid Betz Posts: 14,516
    edited 2011-02-09 16:33
    Dr_Acula wrote: »
    Do you have zog code that has been designed to separate code and data memory? (because I'm not sure Spin or C or Basic can do this).
    This is just using standard features of the GNU linker. You can place .text (the code) into a separate memory area from .data (initialized and uninitialized data). I just place .text in the flash and .data in the SRAM. There is nothing special in ZOG to handle this. It's just the GCC tool chain.
  • localrogerlocalroger Posts: 3,452
    edited 2011-02-09 16:35
    David Betz: The SPI flash chip on the C3 is good for 100k erase cycles

    While that's a lot better than some of the flash out there that's only good for 10,000 cycles, it's not as much as it sounds like. I develop from the bottom up and so through the entire process I am generally rebuilding every 5 to 10 minutes as I test additions and edits. It would really not be unusual for me to rebuild 100 times a day. For a Forth-like environment where the bottom/built stuff doesn't change that's not a problem, but in most compiled languages making a small change can move everything around.

    That means I'd be likely to break the C3 flash limit in about 3 years. That may sound like a lot of use but it really isn't, especially if I have a unit I keep for myself that I use for development of project after project.

    I know another programmer who thought "they'll never weigh a million trucks" and stored the truck count for a highway state scale system in an un wear-leveled EEPROM. This was on a very busy stretch of Interstate 12, and they wore the chip out very regularly at about 6 month intervals. The original manufacturer was shrugging and selling them new main boards for $800 when the counter would stop working. When they called us in and I realized the problem could be fixed for $2 by replacing the EEPROM, the state guys were rather upset with our competitor :-)
  • Cluso99Cluso99 Posts: 18,069
    edited 2011-02-09 17:16
    All the different versions of external memory have their pros and cons. Therefore they each have their own targets, some of which overlap. With the great cooperative efforts on this forum, compatible drivers have been developed so that different methods can be used across a number of platforms. No definitive benchmarks have been done - we are way too busy trying to expand the concepts and code utilising the extra memory. What a hoot !!!

    As for eeprom and flash wearout, it will take a long time. As long as you are aware of the consequences, they are fine to use. For instance, some of the chip manufacturers with inbuilt flash for program memory advise not to send out a "used" development chip. When you do the maths, you really have to do a lot of writes to wear it out.
  • AndreLAndreL Posts: 1,004
    edited 2011-02-09 17:27
    Also, everyone let's remember, flash write cycles, etc. only mean the amount of time before you "might" have to write 2x. That's all. So, I have tested these things and they last about 100,000 before you have to write them 2x, then more or less you just make sure you do a verify after write, which you should do on anything that's important, and then the flash will last more or less forever. So, let's actually do stuff that uses it that much before worrying about it :)

    Andre'
  • localrogerlocalroger Posts: 3,452
    edited 2011-02-09 19:52
    Andre, as far as I am concerned if you write once read back and it's not correct, the chip is ruined. Nobody is going to implement read-verify-rewrite on every operation, because it would be a waste of code to implement and wouldn't buy you all that much. So you extend the chip's life from 100,000 operations to 200,000 operations but every operation takes 3x as long and you burn Hub RAM implementing the rewrite-verify cycle. To me that's a very ugly solution and I'd just use different hardware, which was kind of my original point.
  • jazzedjazzed Posts: 11,803
    edited 2011-02-09 21:57
    Verify is something typically done in manufacturing as a Q/A step or as part of a higher-reliability code update which should have a backup method anyway. It would be insane to do verify in development. Flash is standard in high end routers and other products; there is nothing wrong with using it. Still, removable media which usually has NAND flash provides great flexibility.
  • Cluso99Cluso99 Posts: 18,069
    edited 2011-02-10 01:32
    While I agree with AndreL to a large extent...
    "So, let's actually do stuff that uses it that much before worrying about it :smile:"

    It is good to be mindful of it for a professional application. Also, remember it if you have problems.

    However, unless it is a critical operation, or you expect to burn it out, forget about the verify mode.

    I recall the modifcation we did on the minis I worked on. We devised a modification to disable the read-after-write-verify mode on the disk drives (10MB $16,000 washing machines for you younger people). The speed gain was quite significant. The errors were next to none, and those probably would have been errors anyway.

    The access method and speed is far more important :)
  • David BetzDavid Betz Posts: 14,516
    edited 2011-02-10 09:33
    localroger wrote: »
    David Betz: The SPI flash chip on the C3 is good for 100k erase cycles

    While that's a lot better than some of the flash out there that's only good for 10,000 cycles, it's not as much as it sounds like. I develop from the bottom up and so through the entire process I am generally rebuilding every 5 to 10 minutes as I test additions and edits. It would really not be unusual for me to rebuild 100 times a day. For a Forth-like environment where the bottom/built stuff doesn't change that's not a problem, but in most compiled languages making a small change can move everything around.

    That means I'd be likely to break the C3 flash limit in about 3 years. That may sound like a lot of use but it really isn't, especially if I have a unit I keep for myself that I use for development of project after project.

    I know another programmer who thought "they'll never weigh a million trucks" and stored the truck count for a highway state scale system in an un wear-leveled EEPROM. This was on a very busy stretch of Interstate 12, and they wore the chip out very regularly at about 6 month intervals. The original manufacturer was shrugging and selling them new main boards for $800 when the counter would stop working. When they called us in and I realized the problem could be fixed for $2 by replacing the EEPROM, the state guys were rather upset with our competitor :-)
    I guess I'm not as prolific as you are. I don't think I would tend to reprogram my board more than 10-20 times a day. :-)

    However, I would agree that it probably wouldn't be a good idea to use the SPI flash for any kind of data logging that is likely to write data to the chip constantly. You can reach 100k quite quickly that way!
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