Logic Problem

KaosKidd · 2011-02-02 06:31

Long time ago, my Digital Electronics teacher had us try to design a bio-directional logic circuit using only logic gates. I don't remember if I had done it of finished it, but here I am, with the same problem and I just can't see it through. The goal is:
input a HIGH on A results in a HIGH on B, input a HIGH on B results in a HIGH on A
input a LOW on A results in a LOW on B, input a LOW on B results in a LOW on A.
Bus contention happens if you connect an output to an output.
This is NOT a tri-state device, it must output HIGH or LOW.
You may use VCC and GROUND as needed.
You may also include a Clock signal between 1 and 50 Hz.

The Image LogicGoal.jpg shows the basic connection schema. The devices permissible are shown in the image LogicGates.jpg.

I use Digital Works (v 3.04.39) as my logic simulator to prove any logic. Can someone PLEASE help me resolve this brain bender before I lose what's left of my hair?

KK

davejames · 2011-02-02 07:42

...sounds like a piece of wire would solve the problelm: B follows A, A follows B.

DJ

(just kidding)

PJAllen · 2011-02-02 07:58

Hint/Clue: It's like using two switches to control a lamp, either can turn it off/on.

Leon · 2011-02-02 08:10

KK:

Truth table?

PJAllen · 2011-02-02 08:29

XOR (use NAND gates.)

KaosKidd · 2011-02-02 08:52

I encountered this problem when I was creating a relay circuit for my digital simulator (Digital works only has the logic elements I posted in the first post). The problem surfaced when I tried to connect an output (pin 3 in the attached) to another output (from another relay's pin 3 as a matter of fact), and the simulator reported bus contention, or if the simulation is in progress, a Race condition either of which stop the simulation. In many cases, a logic high can be sent back through a relay (meaning from the NC or NO connection and OUT the common).

What this project is all about is to create a all relay computer (like I've seen in other posts here) in my digital simulator using all relays. I was creating the clock circuit when I discovered this flaw in my relay simulator and I'm at a loss on how to go about getting it right.

Beau Schwabe · 2011-02-02 10:42

Are both sides "A" and "B" required to be symmetric in circuit design?

KaosKidd · 2011-02-02 11:39

Beau Schwabe (Parallax) wrote: »

Are both sides "A" and "B" required to be symmetric in circuit design?

I'm not sure I understand Beau.
The end result is B=A and A=B and either can be an input or output. However, if A is input then B is outout, and if B is input the A is output.

Oh, and thanks everyone for the help / suggestions so far. I'm trying the XOR idea now, but no such luck yet.

KK

Phil Pilgrim (PhiPi) · 2011-02-02 12:02

It seems to me that the only way for a scheme like this to succeed is if the output impedance of the bidirectional logic exceeds that of the devices driving it. Otherwise, the driving device will not be able to force a change in state. As a consequence, I propose a circuit like this one:

attachment.php?attachmentid=77828&d=1296676915

attachment.php?attachmentid=77828&d=1296676915

-Phil

KaosKidd · 2011-02-02 13:00

Phil;
I can't duplicat that in my pure digital simulator

And after spending quite an amount of time in the docs and researching, I think I'm just gonna have to "fudge" the the workings of it...
It's just that I've got this nagging feeling that I'm forgetting something important in all of this...
<sighs> I'll do some more playing...

jmg · 2011-02-02 19:55

You will not be able to solve this in a pure digital simulator.
Take a look at the Bidirectional Isolators, and Translators.

They often use split thresholds and so move into the Analog Domain - this is needed to avoid circular lockup
ie the Logic Zero driven from remote end, Looks like a Logic 0 to Local Digital Loads, but is actually above the back channel threshold
An external drive, pulls the local IP lower than the back channel threshold, and voila, you drive without lockup.

So this is really trinary logic, if you look carefully. : but the digital loads do not look carefully, so they are happy.

Beau Schwabe · 2011-02-02 23:09

Look up "6T SRAM schematic" and treat the wordline as if it's always active. ...and then take another look at the back to back inverter configuration that has been posted.

KaosKidd · 2011-02-03 07:00

Thanks every one for the extreamly helpful replies.
Digital Works stops any simulation when any output is not stable. Thus, the ability to make a relay (A=B) and it's underlying project to make a clock circuit with relays, all within a pure digital realm doesn't work in my simulator. I'll have to come up with an alternat method of duplicating the desired effect. I will, it's just going to take some thought on how to design it all.
As it stands now I have several ideas on how to approch the problem from a different POV. I'll post that later one when I get the details of my "new approch" worked out.
Again, thanks everyone,very much so, for the helpful replies and ideas.

KK

KaosKidd · 2011-02-03 09:35

Well, I tried what I would believe the ultimate test of a true digital solution for this problem.
It would appear to work in the logical terms, but my simulator doesn't permit it to run.
I still get a bus contention error on the in/output lines when ever there's any device's output line connected. I tried.. But, in theory, this should work... I know it's elaborate, and no one would go to such extremes...

Logic Problem

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