C3 SPI Question

richaj45

Hello:

I just read about the C3 card SPI chip select generation.
I noted that the combinatorial decoder outputs are not gated so when the SPI select counter is sequencing there will be decoding glitches on the output of the decoder.

Does anybody think that a little spike on a chip select to a SPI device will make it think it is selected and hang internally waiting for SPI clock even when it was not intended to be selected?

cheers,
rich

RossH

Hi rich,

Seems like a reasonable question. I'm sure AndreL will answer it more fully. However, in the case of SPI RAM, I believe any spurious operations that may accidentally be initiated when the SPI RAM chip is selected by a glitch on the chip select output would be terminated before any harm could be done because the chip is almost immediately deselected again - i.e. a monentary glitch on the chip select would not affect an SPI RAM device. Most likely the same is true for all other SPI devices.

Ross.

Mike Green

The SPI selection scheme on the C3 isn't nice and clean because of what you've noticed, but it should work nonetheless as long as there are no clocks going to the SPI devices (the expected case). Most SPI devices, certainly memory devices and the ADC used, need some commands clocked into the device before they'll do anything. Without clock pulses, the chip select won't do anything that can't be undone when the chip select is removed.

AndreL

No, it won't do anything, remember you have to clock the SPI bus to do anything, and further you have to clock a complete command for anything to happen. So, the beauty of it, is you can glitch the CS lines a billion times, go up, go down, let them settle and then starting clocking. Only the currently selected chip will listen.

Andre'

richaj45

Thanks for the answers guys.

I did not know that about SPI devices and their chip selects.

cheers,
rich

ericball

I'm just surprised that your couldn't find a single chip solution. I thought there was a 74xx chip for everything! (Probably could have done it in a small PLD, but at a higher cost.)

AndreL

There are old CMOS chips that do counting and decode (but this doesn't have anything to do with decoding glitches), but these chips are hard to find, and will go EOL soon. So, I decided to use two chips. Plus, the LVC logic is faster, lower power and easy to find from 100 vendors. On the C3, all I needed was a hard to find chip and be SOL on manufacturing for 2-3 weeks while they find it. I think the 4017, 4022, are the numbers, I would have to look.

Andre'

ericball

Yep, the 744017 has 10 sequentially selected outputs. But I agree with you that it's better to use a solution with easy vendor support.

AndreL

And of course the other thing is packages available and the 4017s are very expensive compared to a standard decoder and counter, so I was at a toss up, but when there are only 2-3 vendors and the cost is >$1 at Q100 that's a hard sell.

Anyway, I might still use the single chip for another design that I do personally, but I try to use really generic stuff when doing designs for other companies, don't want to make parts acquisition harder than it already is

Andre'

Ariba

The 4017 anyway generates active High outputs, so you need a second chip to make the chip selects activ Low.
I see other chip select solutions with a single chip, but it's too late, the design is done...

Andy

AndreL

I think there's a version that has active high and another active low, but yes, done, gone, next thing. Otherwise, I could say, just put the Prop and the whole design on a Altera FPGA

Andre'