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reading/writing to CMOS Static ram — Parallax Forums

reading/writing to CMOS Static ram

ftj405ftj405 Posts: 8
edited 2011-01-21 21:03 in BASIC Stamp
I have an old goldstar cmos 2048 X 8 static ram chip. it is async, and TTL compatible inputs and outputs.

I have a smart card reader and using the example code from parallax have read and written to it, even checked to see if the card is inserted the wrong way.

I'm not sure how to interface to the goldstar chip. trying to think logically, i would think these would be the steps to write to the chip..

1. set the starting address.
2. grab the data and load into a buffer.
3. set the RW flag to write
4 then load...

am i even close? does anyone have any ideas.. thanks
goldstar_1.pdf

Comments

  • Mike GreenMike Green Posts: 23,101
    edited 2011-01-20 20:16
    I'd suggest you stick to something like the Microchip 23K256 SPI Static RAM chip. The chip you have is a parallel chip and requires 11 I/O pins for the address, 8 I/O pins for the data bus, and 3 I/O pins for control (CS, R/W, OE). That's 22 pins for use with a device (the Stamp) that only has 16 I/O pins available. Sure you can tie 6 or 8 of the Goldstar chip's address pins to ground and use 32 or 128 bytes of the memory chip, but that's not very useful. You can also use a pair of 74HC595 serial shift registers to hold a 16 bit value and use those for the 11 bit address and the 3 control lines and that'll need only 3 I/O pins on the Stamp for the 74HC595s and 8 more I/O pins for the data bus.
  • ftj405ftj405 Posts: 8
    edited 2011-01-21 09:58
    thanks for the info. I figured it was a parallel chip by the i/o pins. Since i'm a application developer and not an engineer, i'm gonna take your advice and go with the Microchip ram.

    Tell me what is your opinion on using the parallax micro sd board instead? The project i am working on is a smartcard door lock, so the data that would be stored off the stamp would be simple access list, that would store the userid, date-time of access.

    I want to keep this as simple as possible..

    Thanks for the advice.
  • Mike GreenMike Green Posts: 23,101
    edited 2011-01-21 10:10
    As long as you don't need the high speed of an SRAM, the SD card routine is easy to do. Kye's most recent SD card library (in the Object Exchange here) is well thought out and would let you organize files into directories. Using an SD (or microSD) card would also let you easily create and/or examine the data on a PC.
  • ftj405ftj405 Posts: 8
    edited 2011-01-21 20:51
    Thanks... i ordered both the Microchip SRAM and the sd Card. I'm thinking i could load the SRAM with other data. I have been looking at moving to a propeller chip. Is it possible to read executable code from say SRAM, and run it from the propeller, for example if i had encryption and decryption algorithims executables would i be able to call and run them from a propeller application?

    Thanks again...
  • Mike GreenMike Green Posts: 23,101
    edited 2011-01-21 21:03
    Not the way you think. In other words, the Propeller can not use external memory as an extension of its internal 32K of main (hub) memory. It can access the external memory as an I/O device (which it is to the Propeller). The Propeller uses a combination of native instructions and interpretive code executed by the Spin interpreter which is loaded into a cog from ROM in the Propeller chip. Some people have been working on modifying the ROM interpreter to use external SRAM instead at a modest speed penalty. Some people have been working on other interpreters, some of which keep their programs in external SRAM. Catalina (a C compiler) does this with several variations, each with a different type or amount of external memory and with a corresponding modest speed penalty.

    There are several SD card I/O libraries which allow you to store Propeller programs on the card and load and run them. I wrote an SPI memory library object (in the Object Exchange) that allows you to store files on an SPI flash memory and load and run them. It also allows access to up to two 23K256 SRAMs for storing byte-oriented data.
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