Counter PLL Questions

schwghrt

Hi all,

I'm trying to generate a signal using the NCO mode. No problems there. I'm using a non-factor of 2 value for FRQA. So there is a little jitter. In the AN001 document, there is a footnote that states that using a PLL will reduce the jitter. My question is why?
Is it because

1) you can increase the frequency of the output by up to 16, and reducing FRQA by 16 (so that the final output is the same). Since FRQA is smaller, the jitter is less?,

2) or is it just the nature of the PLL which 'smoothes' out the jitter.

Also, there is a note that states the PLL needs an input of 4 to 8 Mhz. What happens if the input is not within that range?

Thanks

Phil Pilgrim (PhiPi)

The PLL has less jitter, because it's driven by a voltage-controlled-oscillator (VCO) that's locked to the NCO input via a low-pass filter.

Within a range of 4-8MHz, the PLL's VCO operates between 64 and 128MHz. Outside that range, the PLL may not be able to obtain a lock. At NCO frequencies that are too high, for example the VCO will tend to operate at its open loop frequency, which is around 224 MHz (16 x 14MHz).

-Phill

ericball

Further to Phil's explanation, after the VCO is a power of 2 divisor which can divide the VCO output by 1 to 128, which will provide an final output frequency range of 500kHz to 128MHz. IIRC the output is not 100% pure so you may need external filtering of the output depending on your requirements.

The only trick with AN001 is to remember that PLLDIV refers to the divisor of the VCO frequency which is 16x the NCO input frequency.