Using Prop. Video Generator Unit (VGU) AND CTRB counter

homosapien

Hi Folks,

I am attempting to write a section of code that will output a data stream from the VGU while simultaneously generating a clock signal (to be used with the data stream) using CTRB. I have configured CTRA/B similarly, using a different PLL tap to make the clock signal 2x that of the data signal.

The code works - sort of. The problem I have is that the relative phases of the signals are unpredictable, sometimes the clock signal is 'high' during the data hold time, others it is 'high' during the data transition time. (See timing diagram at top of attached code) I have included instructions that restart the counters prior to executing the WaitVid instruction, but this does not seem to help. Anyone have any guesses as to what the issue might be?

Thanks, -h

(OK, for some reason the timing diagram is not showing correctly, although I have been able to cut/paste with Word and Notepad......)

''Want to output test data (VGU) and clock signal (CTRB) so that clock signal always does a low-high transition near
''the middle of the test data bit
''
''       CLOCK    
''
''       DATA     


''Looking with O'scope on clock and data lines I sometimes get the above, but also get this: (inverted clock,
''clock and data transition low-high at same time  :(
''
''
''      CLOCK     
''                                                                               
''       DATA     





       
        org   0              
                        
LCDgen        mov       dira,  outPins           'make outputs

              movi      vcfg,  #%0_01_1_0_0_000   'VCFG set to 8-bit, 4-color).                
              movd      vcfg,  #%000000_000       'pins 7..0 for video output
              movs      vcfg,  #%0_0000_0001    'mask to be used for video output ---->p0 for test              
              mov       VSCLset,  _VSCLset
              mov       vscl,  VSCLset          'mov timing of video output to vscl register

              mov       FREQa,  _FREQa
              movi      ctra,  #%000001_010     'config counterA in video mode (pll) - divisor of 32----> DATA

              mov       FREQb, _FREQb           'load freqb, but do not load into frqb yet (ie dont start ctrb yet)
              movs      ctrb, #1                'set output pin from ctrb - p1
              movi      ctrb, #%00010_010       'config CTRb PLL-single ended - div of 32 ----> CLOCK
              
              mov       pixels,  _pixels  '
              mov       colors,  _colors
              mov       zero,   #0


              
              mov   delay, _delay
              mov   time, cnt
              add   time, delay
              waitcnt  time, delay

              
                
dataOut       mov       tA,     #100

              mov       frqa,   FREQa           'set frequency of CTRa and start running 
              mov       frqb,   FREQb             'set frequency of CTRb and start running
                                                    
:loop         waitvid   colors, pixels              
                djnz    tA,     #:loop
              waitpeq   zero,   #%0000_0010     'wait for p1 to be low
              mov       frqb,   #0              'stop CTRb
              mov       frqa,   #0              'stop CTRa 
              mov       phsb,   #0              'clear CTRb starting value
              mov       phsa,   #0              'clear CTRa starting value  
              jmp       #dataOut     
                                                      

_pixels        long      %0100_0100_0100_0100_0100_0100_0100_0100    '0,1,0,1,0,1 etc          
_colors        long      %1111_1111_1111_1111_1111_1111_0000_0000   ' 0=0's,  1=1's

outpins        long      %0000_1000_0000_0000_0000_0000_1111_1111   'pins that will be used for data and clk's
_VSCLset       long      %0000_0001_____0000_0001_0000       '1clk/pixel - 16clks/frame      '
_FREQa         long      $1000_0000       'PLL freq = 16*(80MHz x $1000_0000)/2^32 = 80MHz
_FREQb         long      $1000_0000
_PHSbStart     long      $1000_0000
_delay         long      10_000_000
_XCLmask       long      %0000_0010              'XCL = p1

pixels        res       1
colors        res       1
VSCLset       res       1
FREQa         res       1
FREQb         res       1
PHSbStart     res       1
time          res       1
delay         res       1
XCLmask       res       1
zero          RES       1
tA            res       1

Phil Pilgrim (PhiPi)

The problem is that the PLL uses a VCO running at 16x the rate of the NCO that feeds it. This clock is divided back down at the chosen ratio to get the desired frequency. But the programmer has no control over which edge of the VCO clock causes a transition in the divided output. That's a function of the value of a hidden internal counter and the tap that produces the PLL's output. You could do a little phase locking of your own at startup by adjusting FRQB up and down in increments while it's running, until the desired phase relationship with CTRA is established. Once that's done, the two clocks should remain in that relationship from then on.

BTW, you don't need to use the so-called "video mode" of CTRA to drive the video circuitry. Any PLL mode will work, in case you also want to assign the output to a pin. This can be handy for generating a dot clock when VSCL is set up for one clock per pixel.

-Phil

homosapien

Hey Phil,

Thanks for the info, I was running out of possible ways to sync the waveforms.

BTW, you don't need to use the so-called "video mode" of CTRA to drive the video circuitry. Any PLL mode will work, in case you also want to assign the output to a pin. This can be handy for generating a dot clock when VSCL is set up for one clock per pixel.

I'm feeling a little obtuse....... Nothing to see here, keep moving......

-h

Phil Pilgrim (PhiPi)

One can hardly be blamed for missing it, since it's not documented anywhere; and the docs that do exist imply otherwise.

-Phil