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I2C Speed — Parallax Forums

I2C Speed

Clive WakehamClive Wakeham Posts: 152
edited 2011-01-10 08:59 in Propeller 1
Hi,
I am currently designing a couple of boards to use with the Propeller chip, and which utilize I2C.

However I have looked at the objects currently available but I can not see any reference to the I2C bus speed which the Propeller is doing with the objects.

The protocol indicates either 100 khz or 400 khz (though devices on the market indicate 1.7 mhz speed).

So does anyone have an idea?

Thanks,

Comments

  • JonnyMacJonnyMac Posts: 9,208
    edited 2011-01-06 23:39
    The Spin objects that a few of us have written are slower than 100kHz; you'd need a PASM driver to get that or 400kHz. Keep in mind that I2C is a synchronous buss so as long as you're under the rated speed for the part you should be okay.
  • Clive WakehamClive Wakeham Posts: 152
    edited 2011-01-07 02:44
    Thanks for that.

    I have noticed a PSAM driver in the Object Exchange for I2C.

    This information helps me in determining which I2C chips I use, since the low power ones run the I2C at 100khz, where as the others at the fast 400khz.

    Thanks again.
  • JonnyMacJonnyMac Posts: 9,208
    edited 2011-01-07 08:55
    Remember, the rating for a component is the maximum buss speed, not the required buss speed.
  • Clive WakehamClive Wakeham Posts: 152
    edited 2011-01-07 13:12
    Ok. Thanks for that.

    I am used to dealing with absolutes.
  • Clive WakehamClive Wakeham Posts: 152
    edited 2011-01-09 21:10
    I have communicated with Dave Hein who created the PASM I2C Driver.

    His object those the following I2C speeds -- with a Delay_Cycle of 52 = 400khz speed, with a Delay_Cycle of 244 = 100khz speed, and with a Delay_Cycle of 14 = 1Mhz speed.

    This gives me the information I needed.

    Regards,
  • Dave HeinDave Hein Posts: 6,347
    edited 2011-01-10 08:59
    The bus speed in the PASM I2C Driver is approximately 400 KHz * 64 / (DELAY_CYCLES + 12) for an 80 MHz system clock. It scales proportionately for other system clocks. It generates an I2C clock with a 33% duty cycle that is high for one-third of the bus cycle and low for two-thirds. This is consistent with EEPROM specs that I've looked at. You might have to run the bus slightly slower if a device requires more than a 33% high time on the clock.
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