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I need some help with a 32 bit PASM divide routine... — Parallax Forums

I need some help with a 32 bit PASM divide routine...

Chris_DChris_D Posts: 305
edited 2010-12-12 02:48 in Propeller 1
Hi folks,

The code fragment below is something I copied off of the forums a while ago - not sure how long ago. I have not idea if it is complete or works yet - I am hoping so because I have no clue how it works or how to do something similar.

Anyway, my question is how many clock cycles will this take to execute? If values matter, the following would be typical of the values I would use...

100,000 / 700

Below is the code I copied from some generous author.

Chris



divide mov temp,#32 ' Divide a 32 bit unsigned dividend
mov remainder,#0 ' by a 32 bit unsigned divisor to
:loop shl dividend,#1 wc ' get a 32 bit unsigned quotient
rcl remainder,#1 ' and a 32 bit unsigned remainder
cmpsub remainder,divisor wc,wr
rcl quotient,#1
djnz temp,#:loop
divide_ret ret

temp long 0
dividend long 0
remainder long 0
divisor long 0
quotient long 0

Comments

  • AribaAriba Posts: 2,690
    edited 2010-12-11 13:12
    The loop has 5 instructions and outside the loop are another 3 instructions. Every instruction takes 4 clocks so the clock cycles are:
    (5 * 32 + 3) * 4 = 652

    If I look at your typical values, then a 32bit / 16bit division may also work. Here is a code from an early Prop Document from Chip:
    ' 
    ' Divide x[31..0] by y[15..0] (y[16] must be 0) 
    ' on exit, quotient is in x[15..0] and remainder is in x[31..16] 
    ' 
    divide          shl     y,#15           'get divisor into y[30..15] 
                    mov     t,#16           'ready for 16 quotient bits 
     
    :loop           cmpsub  x,y     wc      'if y =< x then subtract it, quotient bit into c 
                    rcl     x,#1            'rotate c into quotient, shift dividend 
                    djnz    t,#:loop        'loop until done  
    divide_ret      ret                     'quotient in x[15..0], remainder in x[31..16] 
    

    This needs only (3 * 16 + 3) * 4 = 252 clock cycles

    Andy
  • Chris_DChris_D Posts: 305
    edited 2010-12-12 02:48
    Ariba,

    Thank you very much. I see too how you figured out the number of times through the loop, that was what I had not idea how to determine.

    Yes, the full range of my divisor value will fit in 16 bits so your suggestion will save me a lot of cycle time!

    Chris
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