PING Communication Protocol

shaunee

I plan on controlling the PING sensor with a FPGA. In coding the driver, I need clarification on the PING's communication protocol. Is the Echo Holdoff time (t_HOLDOFF = 750us) exact, or an approximate value? ie. Can I wait for 750us after I lower the Input Trigger Pulse and then just count until the falling edge of the Echo Return Pulse t_IN? Or do I have to detect the rising edge of t_IN and start counting from there?

Mike Green

The holdoff time is not exact. You need to detect the rising edge of the echo timing pulse and count off from there.

shaunee

Thanks for the quick reply, Mike. Another timing question: how exact are the other timing parameters - tIN-MIN, tIN-MAX, Delay before next measurement? My FPGA counts in ns, so how much time should I allow for these parameters (115us, 18.5ms, 200us respectively) to deviate and still be valid? eg. Is +/- 1us long enough? Timing is important since I plan on driving multiple PING sensors sequentially in as short a time as possible.

Mike Green

These parameters are simply not characterized to that sort of resolution. The PING))) was developed originally for use with a Stamp which has (interpretive) instruction times on the order of 100us and can do pulse width timing to a resolution of 2us using the PULSIN statement.

Just guessing, I'd allow +/- 10% variation in the timings you mentioned and I'd not be surprised if they varied more than that. You're not going to be able to drive multiple PING)))s as quickly as you want because of echos. One PING)))'s dying echos can easily trigger another PING))) if you don't allow enough time. I'd allow for several times the maximum range. We're talking maybe one reading every 50 to 100ms.

shaunee

Okay, now that I've got the specs on the timing, I need the specs on the voltage levels. The datasheet says that the "Bidirectional TTL pulse interface on a single I/O pin [SIG] can communicate with a 5 V TTL or 3.3 V CMOS microcontrollers." But then it goes on to say that the Input Trigger and Echo Pulse are both positive TTL. But both these signals reside on the SIG pin. Given that the PING uses a +5 VDC supply, what are the voltage thresholds for the SIG pin? ie. min/max Vin/Vout for logic High/Low : Vinhigh, Vinlow, Vouthigh, Voutlow. My FPGA can interface w/ LVTTL and LCMOS devices, but depending on these thresholds, I may need a voltage translator.

Mike Green

Sorry, I can't give you any kind of definitive answer. I suspect that the SIG pin has a pullup of some value to Vdd, whether that's 3.3V or 5V. The controller on the PING is CMOS, so the voltage threshold for input signals is probably 1/2 of Vdd. The low output voltage is probably 0.3V (typical for CMOS).

If you need a better answer than that, you'll have to call Parallax Tech Support and they'll have to check the schematic which is not publically available.

shaunee

Here's the response I got from Tech Support about the SIG pin:
"What we know works for the minimum input is 3.3V. You may test for lower voltages if you like but that's what we say is the minimum. It will still signal back at 5VDC even if you trigger at a lower voltage. Yes [PING], only runs on +5VDC."
So I will need a voltage translator.