Can the reset line be held down for a long time?

Toby Seckshund

On a board, that I am about to play with, I might want to hold the Prop in reset whilst a CPLD is programmed via its JTAG. Would this be a good way to effectivly tri-state the Prop, or would it get bored and start to do things?

Mike Green

The Prop is a static logic chip. That means that the clock can slow down to zero and nothing "funny" would happen (other than things stopping). Similarly, /RES is level sensitive. When it goes low, the Prop stops and resets. When it goes high, 50ms later, the Prop goes into its startup process. There's no limit to how long the Prop can wait with /RES low. This is all implied by the information provided in the Propeller Datasheet.

Toby Seckshund

Thanks Mike, that is what I expected. (As I posted and wandered off, I thought a RT*M would be the answer)

I just thought I would ask the simple question to those who have far more experience with the Prop. I didn't want it to get playing with the CPLD's pins whilst it was being JTAGed. I suppose that the next question would be "Would the CPLD care if the pins were being altered during programing?".

I could remove the PLCC from its socket for programming but in circuit would be more convienient.

Mike Green

During reset, the Propeller's I/O pins are all set to input mode. That means they're high impedance. You'd have to check the CPLD datasheet to see what is expected during programming. I would assume, unless the datasheet says that the CPLD I/O pins have to remain stable, that the CPLD ignores them during programming. It's probably not an issue, but the CPLD I/O pins are considered floating when the Prop is in Reset and, unless there are pullups or pulldowns, the state of the I/O pins may fluctuate anyway.

Toby Seckshund

As long as they play nice, all will be well. The JTAG pins are not shared so as long as the P0-P11 pins are Hi-Z then I will be ok. In cct programing is so common I guess that it will cause no upsets.