Obviously, this needs some more thought - for example, waitxxx and cogxxx need to be examined for potential bad effects...
Fortunately, the 23 bits available with all top 9 bits being 0 shifted left two positions due to long alignment give a 32MB (8MLong) address space, and I am sure we can still recover some bits from the top bits of instruction encoding.
Perhaps a better method would be to use 0000 for the condition bits, then by using
ROL address,#11
we would have a 1GB (256MLong) address space... with all conditions zero, none of those pesky WRxxx could cause a problem.
Mind you, this could be a problem on Prop2 if Chip used some of the NOP patterns...
It could well be possible to just ensure the top 4 bits are "0001" which gives 28 bit address space (256MB IIRC without working it out). This would decode to the unused prop instructions mul/muls/enc/ones. Obviously this needs checking to ensure the prop does indeed ignore these op codes. I am sure Chip would answer if this is needed.
This would decode to the unused prop instructions mul/muls/enc/ones. Obviously this needs checking to ensure the prop does indeed ignore these op codes.
Unless nr is specified those instructions clear the destination register.
Comments
Obviously, this needs some more thought - for example, waitxxx and cogxxx need to be examined for potential bad effects...
Fortunately, the 23 bits available with all top 9 bits being 0 shifted left two positions due to long alignment give a 32MB (8MLong) address space, and I am sure we can still recover some bits from the top bits of instruction encoding.
Perhaps a better method would be to use 0000 for the condition bits, then by using
ROL address,#11
we would have a 1GB (256MLong) address space... with all conditions zero, none of those pesky WRxxx could cause a problem.
Mind you, this could be a problem on Prop2 if Chip used some of the NOP patterns...
Unless nr is specified those instructions clear the destination register.