Please help: TEST instruction operands not interchangeable ?

bogdanm

Hi list,

Apologies in advance if I'm asking something stupid/obvious, but I'm quite new to the propeller and this problem has been driving me crazy for some days now (until I found it). I connected a SPI SRAM (23k640) chip to the propeller, using the SPI ASM object (http://obex.parallax.com/objects/431/). It worked without problems. Then I tried optimizing the SPI object (I need more speed) and couldn't make it work, I was always reading "0" from the RAM. After a lot of debugging, I traced the problem to a "test" instruction. The problem is reproducible with the original SPI ASM object too: if I change this line (in red below):

MSBPRE_                                                 ''     Receive Data MSBPRE
MSBPRE_Sin    [color="red"]test    t1,             ina     wc[/color]       ''          Read Data Bit into 'C' flag
              rcl     t3,             #1                ''          rotate "C" flag into return value
              call    #PreClock                         ''          Send clock pulse
              djnz    t4,             #MSBPRE_Sin       ''          Decrement t4 ; jump if not Zero
              jmp     #Update_SHIFTIN                   ''     Pass received data to SHIFTIN receive variable

with this line:

MSBPRE_                                                 ''     Receive Data MSBPRE
MSBPRE_Sin    [color="red"]test    ina,             t1    wc[/color]       ''          Read Data Bit into 'C' flag
              rcl     t3,             #1                ''          rotate "C" flag into return value
              call    #PreClock                         ''          Send clock pulse
              djnz    t4,             #MSBPRE_Sin       ''          Decrement t4 ; jump if not Zero
              jmp     #Update_SHIFTIN                   ''     Pass received data to SHIFTIN receive variable

the code doesn't work properly anymore.
I looked through the manual, but I can't find any reason for the TEST instruction to work differently when its arguments are interchanged. It should just do a logical AND of its arguments and then set the carry flag, so why does the order of the arguments matter? I know I'm missing something painfully obvious here, but what is it ?
Thanks for your help.

kuroneko

If you use ina in the destination slot of an instruction then you'll access the shadow register and not the actual I/O input data. See data sheet chapter 5.2 Cog RAM, Note 1. So for your test instruction you'll have to stick with test mask, ina wc.

bogdanm

Thank you very much, I completely missed that part. Should've been more careful.

Mike Green

It has nothing to do with the TEST instruction. In the description of the various special registers, there's a comment about some being read-only and some being read/write. INA is read-only and, like other read-only special registers, won't work as expected if you specify it in the destination field (left-hand operand).

What happens is that there's actually cog memory underlying all of the special registers and there's special hardware that substitutes a particular hardware register for particular cog memory locations. There's one set of special hardware for the source field and one set of special hardware for the destination field regardless of the instruction itself. Instruction fetches always come from cog memory ... there's no special hardware for that.

When you put INA in the destination field, you're referencing the "shadow memory" location that underlies INA, not INA itself.

bogdanm

Thanks Mike. Lesson well learnt