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Propeller 2 Preliminary Feature List — Parallax Forums

Propeller 2 Preliminary Feature List

BumpBump Posts: 592
edited 2012-11-24 01:05 in Propeller 1
I do believe this is relevant to your interests:
http://www.parallax.com/Propeller2FeatureList/tabid/898/Default.aspx

Enjoy!
«134

Comments

  • mwalimumwalimu Posts: 44
    edited 2010-10-22 11:47
    Cool!!!!!!
  • mwalimumwalimu Posts: 44
    edited 2010-10-22 11:49
    When referring to RAM and ROM, is that 128k bytes or 128k x 4 bytes, same for ROM (32k bytes or 32kx 4 bytes)?
  • Heater.Heater. Posts: 21,230
    edited 2010-10-22 11:56
    It says: "Main memory: 128 KB RAM(2) + 32 KB ROM planned"

    That's Kilo Bytes.

    It says "Optional external 32-bit addressable SDRAM for run-time data workspace; code space is not extendable"

    I say, pah!. Zog is going to love running megabytes of C code from that external RAM. As is Catalina and Java and whatever other systems there are cooking.
  • Heater.Heater. Posts: 21,230
    edited 2010-10-22 11:58
    Oh, and thank you, we do enjoy:)
  • CampeckCampeck Posts: 111
    edited 2010-10-22 12:07
    whooooa!!!
    ADC's DAC's comparators oh my!
    and 1.28 BIPS! crazzzy !

    I need to hurry up and figure out how to program the Prop 1 so I can jump to the Prop 2!
  • RaymanRayman Posts: 14,669
    edited 2010-10-22 12:09
    I like the 1080p :)
  • Bill HenningBill Henning Posts: 6,445
    edited 2010-10-22 12:11
    Very nice... but I am worried about Note(2)... I would not be happy with <128K hub memory

    And we all want more details on the SDRAM support :)
    Bump (Parallax Inc) wrote: »
    I do believe this is relevant to your interests:
    http://www.parallax.com/Propeller2FeatureList/tabid/898/Default.aspx

    Enjoy!
  • nicolad76nicolad76 Posts: 164
    edited 2010-10-22 12:13
    when was that page updated last time? :)
    Prop2 is in dvanced stage of design so many specs might have changed, right?
  • SapiehaSapieha Posts: 2,964
    edited 2010-10-22 12:15
    Hi Bump.

    Sorry as I need say that.
    I'm surprised BUT not directly in positive way.

    It is to many questions still not answered.


    Bump (Parallax Inc) wrote: »
    I do believe this is relevant to your interests:
    http://www.parallax.com/Propeller2FeatureList/tabid/898/Default.aspx

    Enjoy!
  • Daniel HarrisDaniel Harris Posts: 207
    edited 2010-10-22 12:18
    nicolad76 wrote: »
    when was that page updated last time? :)
    Prop2 is in dvanced stage of design so many specs might have changed, right?

    Actually, this is the clearest picture we have. This document was written last week after talking with Chip and Jeff directly.
  • Daniel HarrisDaniel Harris Posts: 207
    edited 2010-10-22 12:19
    Sapieha wrote: »
    Hi Bump.

    Sorry as I need say that.
    I'm surprised BUT not directly in positive way.

    It is to many questions still not answered.

    What questions do you still have Sapieha?
  • BumpBump Posts: 592
    edited 2010-10-22 12:23
    Ah, I'll put a date stamp on the page to show when it was last updated.

    Also, a small change was made if you've already checked/downloaded the .pdf

    Under 'General: ... Planned 128-Pin Package(1)'
    Now reads 'General: ... Planned 128-Pin SMT Package (1)'
  • SapiehaSapieha Posts: 2,964
    edited 2010-10-22 12:32
    Hi Daniel Harris (Parallax).

    In entire description it is no any WORD about Input speed possibility.
    1. --->
    As I mentioned from start I tested first Propeller I it is nice to have relatively fast Output speeds on PIN's but if it is not track by same speed on INPUT pin's side ---> It is waste of silicon.

    Same question track to Counters.

    2. ---> Serialiser
    3. ---> Strobed IO's with Read/Write signaling
    4. ---> Extra MEM in COG's that can be used in that way Chip described and other ways we can FIND of theirs usage.

    AND more

    Daniel Harris (Parallax) wrote: »
    What questions do you still have Saphieha?
  • ericballericball Posts: 774
    edited 2010-10-22 12:36
    IMHO greater clarification is required on the enhancement from Propeller 1:
    1. SDDRAM and SD card - hardware or software I/O?
    2. 100 I/O pins! How are they controlled? (Must be more complex than DIRx/OUTx/INx.)
    3. What are the dedicate 8 pins used for during boot? (SPI, serial & SD?)
    4. Heck, details on everything on the right side.
  • K2K2 Posts: 693
    edited 2010-10-22 12:46
    Optional external 32-bit addressable SDRAM for run-time data workspace

    Perfect!!! I had hoped, but reality is far better!
  • Roy ElthamRoy Eltham Posts: 3,000
    edited 2010-10-22 14:14
    There's no mention of the texture mapping instruction or the color palette memory on each cog.

    Are they gone?
  • Bobb FwedBobb Fwed Posts: 1,119
    edited 2010-10-22 14:31
    ericball wrote: »
    2. 100 I/O pins! How are they controlled? (Must be more complex than DIRx/OUTx/INx.)
    Sure it can be. It's only 96 pins, so that's 3 banks of 32. So simply DIRA/B/C, OUTA/B/C, INA/B/C. Just like they had planned it all along for when they got a 64 IO package (with the B bank).

    How they will actually do it, I don't know, but that is the simplest, and it would make code more backward compatible.
  • jazzedjazzed Posts: 11,803
    edited 2010-10-22 15:24
    Bump (Parallax Inc) wrote: »
    I do believe this is relevant to your interests ....

    Yay Bump! Looks great! :)
  • HarleyHarley Posts: 997
    edited 2010-10-22 16:47
    Wow! This will make a great read/absorb for the weekend.

    Thanks to all @Parallax for providing such a list way in advance of having silicon in OUR grubby hands. Wonder how many other companies have done such an early release?

    I and others sure were hoping for such a view.
  • User NameUser Name Posts: 1,451
    edited 2010-10-22 17:14
    Sapieha wrote: »
    3. ---> Strobed IO's with Read/Write signaling

    No sense in using SDRAM if there isn't R/W signaling. If Prop2 were just like Prop1 in this regard, they wouldn't have mentioned external RAM at all.
  • BeanBean Posts: 8,129
    edited 2010-10-22 18:25
    I thought the I/O pins were going to have pull-up and/or pull-downs ?
    Did that get cut ?

    Bean
  • RavenkallenRavenkallen Posts: 1,057
    edited 2010-10-22 21:20
    Very interesting....i still(Hopeless, i know) wish that it was somehow available in a DIP package. Perhaps, someone will quickly create a Propstick 2 sort of thing(It it will probably be expensive though)...This may sound like a stupid question, but the increase in speed will also affect programs written in SPIN? Right?
  • potatoheadpotatohead Posts: 10,261
    edited 2010-10-22 21:38
    Yes. The interpreter will execute instructions quicker. That could be balanced out by making Spin 32 bit. We had a discussion on addressing, and the general conclusion of it was to open Spin up now, so that it won't have to happen again in the future, for say Prop III.

    Seems to me, the net product of that will be faster Spin programs, but not as small of ones as we get now.

    BTW: Looks pretty sweet to me! It's all going to be a very nice boost over Prop I. Can't wait. ...err, well I can, but don't want to. :)
  • hinvhinv Posts: 1,255
    edited 2010-10-22 22:24
    I like the crystal spec. It looks like we will be able to use common 25MHz crystals X8 to overclock it to 200MHz if it will do it.
  • Heater.Heater. Posts: 21,230
    edited 2010-10-23 00:18
    User Name,
    No sense in using SDRAM if there isn't R/W signaling.

    This is a good point. I don't believe that Prop II will have a bus as such for any particular memory technology. Rather it will offer hardware assistance for creating such buses with a little software help.

    In which case the feature on offer is not really "SDRAM support" but rather a bunch of features in the I/O system that can help with such devices.

    We want to know more....

    I do hope there is some high speed serial I/O possibilities, serializer/deserializer, that can be used to enable fast communication with external devices and other Prop II's
  • John A. ZoidbergJohn A. Zoidberg Posts: 514
    edited 2010-10-23 00:48
    I was hoping it is in DIP package version too, but with less pins, only the DIRA is available. The onboard hardware multipliers/dividers are irresistable though.

    Please keep us updated, and I will try one of these Prop II once it is out! :)
  • SapiehaSapieha Posts: 2,964
    edited 2010-10-23 02:25
    Hi User Name.

    YES ---> But will that R/W signaling be possible to handle standard 8-Bits wide I/O IC's.
    As You maybe know to THAT needs some control of wait time for that signals. Else it will be no much usable

    User Name wrote: »
    No sense in using SDRAM if there isn't R/W signaling. If Prop2 were just like Prop1 in this regard, they wouldn't have mentioned external RAM at all.
  • Cluso99Cluso99 Posts: 18,069
    edited 2010-10-23 03:55
    Bump: Thanks for the info.

    I am a little disappointed with 128KB Hub RAM and 32KB Hub ROM. This will mean basically no new ROM code space so I expect we will lose some of the existing ROM code and this may mean sometimes the old ROM code will now have to use RAM space.
  • Heater.Heater. Posts: 21,230
    edited 2010-10-23 04:14
    Yeah, and no space for a ZPU interpreter in the ROM:(
  • AleAle Posts: 2,363
    edited 2010-10-23 06:41
    We do not know what is in that ROM. With a CORDIC machinery inside the tables may be gone.... and then there is a lot of free space in ROM !.

    OTOH only 128 KB HUB RAM :(.... but the idea of using a SDRAM to extend the HUB space makes everything moot... I mean the "there is not space for" :) and 32 bit wide !!!!! That will be s
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