Bizzare Timing
This has been bugging me for a while and I can't seem to find the answer. This always returns 160M cycles instead of 80M cycles like I thought it should. Instead of P16 being high and low for 1 second it is 2 seconds. It seems that dT is added twice somewhere. What am I doing wrong?
CON
_CLKMODE = XTAL1 + PLL16X
_XINFREQ = 5_000_000
Pin = 16
OBJ
DEBUG : "FullDuplexSerial"
VAR
long T, dT, oldT
PUB Main
dira[Pin]~~
DEBUG.start(31,30,0,115200)
dT:=clkfreq
T:=cnt
T+=dT
repeat
if (||(||cnt - ||T) => dT)
!outa[Pin]
oldT:=T
T:=cnt
T+=dT
DEBUG.dec(||(||T - ||oldT))
DEBUG.tx(13)

Comments
Bean
pub main | dt, t, delta debug.start(31, 30, %0000, 115200) dira[pin] := 1 dt := clkfreq t := cnt repeat delta := ||(cnt - t) if (delta > dt) !outa[pin] debug.dec(delta) debug.tx(13) t += deltaIf statement is true
Pin is toggled
T is set to current cnt
Add 80M to T
Current cnt + dT should be one second.
So it should be high for 1 second and low for 1 second (0.5Hz).
What is it that I don't see?
I understand that it is not good time keeping but I am not getting 0.5Hz, I am getting 0.25Hz with my original code.
So you should remove the T+=dT (in and outside of the loop -- or just the T:=cnt inside the loop :-P).
Got it. Thank you.
T = cnt_old + dT
(cnt_new - T) => dT
cnt_new - (cnt_old + dT) => dT
cnt_new - cnt_old - dT => dT
cnt_new - cnt_old => 2dT