How does the Prop solve this timing problem?

John Kauffman

One theoretical question has stuck in my mind since I first saw the schematic of the Prop architecture. In a case where small amounts of time are crucial, what if the hub is pointing to cog 4 and at that very moment, cog0 needs to change a pin? It can't change the pin until the hub comes around to cog0 and by that time it might be too late for timing in Cog0's program.

I can think of two possible solutions that might have been used.

Solution 1 - When cog4 starts and has a pin assignment then that pin is not available to other cogs and cog4 can change the outa[] on its pin regardless of where the hub is currently pointing. In terms of outa[], cogs are independent of the hub.

Solution 2 - The hub 'spins' so fast that it gets from cog to cog quick enough to keep within tolerances of timing for even the fastest and most time-sensitive applications.

Can someone explain how the Prop solves the problem? Thanks.

Phil Pilgrim (PhiPi)

Pin access is not subject to hub timing. Each cog has direct access to the pin logic.

-Phil

John Kauffman

Thanks, Phil. I should have asked a year ago so it wasn't on my mind.

So if two cogs try to change the same pin:
- programmer's responsibility to not commit that error?
- prop locks pins into a given cog control?

Mike Green

1) The only instructions subject to hub timing interlocks are those for accessing hub memory. If you don't access hub memory, just cog memory, instructions continue on, with most of them taking 4 clock cycles per instruction. Other hub instructions like WAITxxx and LOCKxxx have their own timing restrictions that are spelled out in the datasheet.

2) I/O access has no timing restrictions. There's a block diagram that shows how the I/O pins are connected to each cog and each cog has its own set of I/O registers. These are OR'd together and any cog can change an I/O pin by changing the cog's I/O registers at any time. If any cog sets its DIR register bit to 1, that I/O pin is treated as an output. If any cog whose DIR register bit is 1, sets the corresponding OUT bit to 1, that I/O pin is set high, otherwise it's set low. This is accomplished with the OR gate chain shown in the block diagram.

Andrey Demenev

LOCKxxx, COGxxx and CLKSET are hub instructions, just like RDxxxx and WRxxxx, and have exactly the same timing - 7 to 22 cycles depending on hub access window position

mpark

Andrey Demenev wrote: »

LOCKxxx, COGxxx and CLKSET are hub instructions, just like RDxxxx and WRxxxx, and have exactly the same timing - 7 to 22 cycles depending on hub access window position

8 to 23 cycles now. See http://forums.parallax.com/showthread.php?t=125451