A good challenge for you is my heater_fft. There is a Spin and a PASM implementation in there. Extra credit for splitting the fft over multiple cogs for more speed. FFT is usefull in that it can be easily be parallelized. Extra-extra credit for splitting it over multiple propellers and showing a sped up.
Took a peek in Heater's fabulous FFT demo. It really looks good as a benchmark, but the new problem I am confronting now is that Heater's FFT generator (heater_fft.spin) got two favors, SPIN and Assembly. I may have to use two Out-of-Order execution methods, Branch Prediction Reordering and Discard Issue.
The options just rapidly dwindle when confronting with SPIN.... I may write the SPIN JITC (Just-in-Time Compiler), but then it's not going to be easy, starting with the inefficient SPIN emulator already written in the on-die first-stage boot firmware (V 1.0)....
Right now, I have been looking around on Wikipedia out of boredom: I have found few that I took into account in my previous PDFs.
One very infamous "memory wall" - Von Neumann Bottleneck.
Another one, prolongation delay in the wiring.
Yet, I have been thinking about putting in the FPGA in the final revision which will turn out to be the best action to perform, because of Von Neumann bottleneck: The faster the XMOS transputer or Parallax Propeller transfer the data, the bigger the memory wall gets.... Even 8 Propeller II interconnected to a FPGA would outrun the SDRAM cache, thus it just get difficult to keep the Propeller II chips happy while being able to hold down the sustained IO speed. GDDR3 seems to be the best option, the only issue is, not every FPGAs know how to deal with the higher-speed RAM originally designed for video processor hardware.
Another still, the wiring inside the circuit used not to matter much - at least in the older supercomputers, such as the one fitted with InMOS Transputers T414, as the FSB out of those CPUs were of fairly low frequency - about 15MHz. Now, not so simple anymore. We're seeing the AMD Hypertransport pipelines and Intel QuickAssist pipelines approaching 4 GHz, and the RAMs slowly creeping to 2 GHz - the wiring parasitic resistances and trace size starts to matter much more. The only two methods to counter that IO prolongation delay issues are: Trace-matching on PCB designs and / or IO delay training.
And, sorry if I didn't mention any of those words in the PDFs, they're similar to what I wrote in the PDF.
In order to have the best supercomputing experience, I must emphasize again:
1. Take Von Neumann bottleneck between the RAM and processors into account. (You can use SRAM or SDRAM as a cache RAM linked to the processor to help reduce that problem by 1 / 2 or 1/3 - depending on the configuration but for the FPGA being used as a context switch, it is preferred to have at least 256MB higher speed RAMs so that way the FPGA's CPU core don't get overwhelmed.)
2. Ensure that the same firmware codes are used in all of the microcontrollers being placed into the circuit, but assign the ID each into the firmware ROM ID tags, that way the seed processor and the other processors probably on the same circuitry as the particular microcontroller "CPU" being summoned upon, so that way it is known for it to be delivered to the correct chip.
3. Pick and choose. Just pick the best part such as FPGA as possible to match the necessary bandwidth requirement (With 8 P8X32A chips, it is easy. But with eight Propeller II chips, it would become a sort of bandwidth nightmare...)
4. Get the RTOS (FreeRTOS or uCLinux for example) and configure it for preemptive "hook and trunk" callback so that way the necessary numbers of P8X32A can be called into the action in the simple way or your preferred way of requesting the service - at least for some people, Linux is straightforward to be configured. You can always build one from scratch if you prefer.
5. Always be sure you get the strongest Switchmode power supply possible. ATX SMPS are easier to obtain, but you need to be sure, by multiple the worst-case scenario current consumption of an individual processor and multiple by the processors you are going to use - that way you will be able to get what you need what you can offer yourself a headroom. Ex: A P8X32A can have max consumption of 300mA and you want to use 20 or 80 chips. Multiply its consumption by the number of chips = 300mA x 20 chips = 6 Amps (10A headroom recommended) and 300mA x 80 chips = 24 Amps (65 Amps headroom recommended). You gotta give yourself some headroom when dealing with it. And, if you go with switchmode voltage regulator, I would prefer for to go with 12 Volts rail to be regulated down to 3.3 or 1.8 Volts, that way you won't accidentally melt the insulators off the wires.
Note: It is not just for Propeller II based supercomputer hardware, it does apply to every hardware, including the XMOS XS1 transputer based array supercomputer. Even PIC32. You just have to ensure that every little things work first then you can go ahead and pump the data into it - that way you will know it works fine and is stable. Number 5, about an OS, isn't going to matter anyhow, you would still need a way to feed the data into it and receive the results out from the hardware.
I may still use XMOS XS1 for an auxiliary board - still planning out the Propeller II based hardware to ensure it is the way I want to go with, and to be able to achieve the highest performance as possible.
Why XS1? It's the nature of the transputers that would lend to when the Propeller II arrays becomes stressed, the XS1 can pick off the GDDR3's content and to reduce the stress - I also noticed on the XCORE forums, they take the punishments pretty reasonable. You can stuff lot of stuff without strangling this chip. I am going to use it as a backup processor - I can choose between CPU type in the menu anyways. That way it's made simple when I am dealing with every environment, even the rapidly-changing ones.
Right now, I have been looking around on Wikipedia out of boredom: I have found few that I took into account in my previous PDFs.
One very infamous "memory wall" - Von Neumann Bottleneck.
Another one, prolongation delay in the wiring.
Yet, I have been thinking about putting in the FPGA in the final revision which will turn out to be the best action to perform, because of Von Neumann bottleneck: The faster the XMOS transputer or Parallax Propeller transfer the data, the bigger the memory wall gets.... Even 8 Propeller II interconnected to a FPGA would outrun the SDRAM cache, thus it just get difficult to keep the Propeller II chips happy while being able to hold down the sustained IO speed. GDDR3 seems to be the best option, the only issue is, not every FPGAs know how to deal with the higher-speed RAM originally designed for video processor hardware.
Another still, the wiring inside the circuit used not to matter much - at least in the older supercomputers, such as the one fitted with InMOS Transputers T414, as the FSB out of those CPUs were of fairly low frequency - about 15MHz. Now, not so simple anymore. We're seeing the AMD Hypertransport pipelines and Intel QuickAssist pipelines approaching 4 GHz, and the RAMs slowly creeping to 2 GHz - the wiring parasitic resistances and trace size starts to matter much more. The only two methods to counter that IO prolongation delay issues are: Trace-matching on PCB designs and / or IO delay training.
And, sorry if I didn't mention any of those words in the PDFs, they're similar to what I wrote in the PDF.
In order to have the best supercomputing experience, I must emphasize again:
1. Take Von Neumann bottleneck between the RAM and processors into account. (You can use SRAM or SDRAM as a cache RAM linked to the processor to help reduce that problem by 1 / 2 or 1/3 - depending on the configuration but for the FPGA being used as a context switch, it is preferred to have at least 256MB higher speed RAMs so that way the FPGA's CPU core don't get overwhelmed.)
2. Ensure that the same firmware codes are used in all of the microcontrollers being placed into the circuit, but assign the ID each into the firmware ROM ID tags, that way the seed processor and the other processors probably on the same circuitry as the particular microcontroller "CPU" being summoned upon, so that way it is known for it to be delivered to the correct chip.
3. Pick and choose. Just pick the best part such as FPGA as possible to match the necessary bandwidth requirement (With 8 P8X32A chips, it is easy. But with eight Propeller II chips, it would become a sort of bandwidth nightmare...)
4. Get the RTOS (FreeRTOS or uCLinux for example) and configure it for preemptive "hook and trunk" callback so that way the necessary numbers of P8X32A can be called into the action in the simple way or your preferred way of requesting the service - at least for some people, Linux is straightforward to be configured. You can always build one from scratch if you prefer.
5. Always be sure you get the strongest Switchmode power supply possible. ATX SMPS are easier to obtain, but you need to be sure, by multiple the worst-case scenario current consumption of an individual processor and multiple by the processors you are going to use - that way you will be able to get what you need what you can offer yourself a headroom. Ex: A P8X32A can have max consumption of 300mA and you want to use 20 or 80 chips. Multiply its consumption by the number of chips = 300mA x 20 chips = 6 Amps (10A headroom recommended) and 300mA x 80 chips = 24 Amps (65 Amps headroom recommended). You gotta give yourself some headroom when dealing with it. And, if you go with switchmode voltage regulator, I would prefer for to go with 12 Volts rail to be regulated down to 3.3 or 1.8 Volts, that way you won't accidentally melt the insulators off the wires.
Note: It is not just for Propeller II based supercomputer hardware, it does apply to every hardware, including the XMOS XS1 transputer based array supercomputer. Even PIC32. You just have to ensure that every little things work first then you can go ahead and pump the data into it - that way you will know it works fine and is stable. Number 5, about an OS, isn't going to matter anyhow, you would still need a way to feed the data into it and receive the results out from the hardware.
Wow, Dr. Mario, very nice! Your postings are like chapters in a Machine Bible to follow along and gain advice for all good things regarding these projects. It's great that we can apply the technology, methods and results of one chip with others of varying types.
I have found that the maximum amperage draw from Partitions of 50 propeller chips, or 5 in the tester, or over a hundred in the the multiple Partitions can vary significantly. I have been wow'd numerous times with the same circuit, because it went from software A to software B with varying cog work demand, which resulted in massive changes in current draw. The smaller "Brain Child," with five Propellers, could increase from 5ma to 40ma for example just by changing out computational software. I've gone easy on this being careful never to exceed 2 amps in three partitions. But this could change when unleashing the full simultaneous multi-chip computational power. You only need to run some programs that do different levels of processing to observe the effects. This could be a study in itself. I had hoped someone would do the study and give some guidelines about which functions draw what power.
Indeed the Transputer is an amazing machine and literally many genius' worked to design and implement it, and it remains as a great inspiration to all of us today. It's remarkable we can still find elements of the original company. I think we have a lot to learn from the initial waves of paralleled technology for the 40s and 50s and can apply such technology in new ways.
The Propeller's power draw is actually pretty straightforward. For a particular clock frequency each cog draws a certain amount of power when it is running, less when it is in a wait state (waitcnt, waitpeq, etc.), and practically nothing when it is cogstopped. It's all in the P8X32A spec sheet.
At full bore, at 80 MHz and all 8 cogs running, a Propeller draws about 200 milliamps at 3v3. This doesn't count power dissipated in the I/O circuitry. An overclocked Prop probably draws more and the main reason for the spec being 80 MHz might be that while yes, you can overclock the Prop, if you do and you run full bore on all 8 cogs you might overheat the chip. Max ratings are usually meant to include any abuses you might sneak in and with the 8-cog architecture you have a lot of room to sneak in under the worst case with an abuse.
"What constitutes running" is actually pretty simple. Cogs are always either stopped, running, or waiting. If a cog is doing nothing more computationally intensive than sitting in an infinite JMP #$ PASM loop it will draw the same power as one doing a fourier transform. Cogs in wait states draw much less power, and those not running hardly any.
It's best to give yourself some headroom so you won't either melt the insulators off the wires or blow up the power supply (the cheapest SMPS usually explode if it doesn't trip quickly enough - a bit expensive one like the Ultra Modular power supply I have in my computer would just shut down immediately once the overload is noticed). You will still want to use the inverter-based voltage regulator or a LDO with 300 to 1,000 milliamps circuit breaker built-in so you won't cook the P8X32A - something to take into an account (like in the Propeller manual). Lastly, you may have to plug in few wires together for a higher-ampere rail, or best yet, use a thick gauge wire for that kind of current (IDE cable usually can only handle 10A before they overheat - at 20A, you're asking for trouble...)
And, also you would want to put in fan if you want huge number of QFN-44 chips in a cabinet so you won't have to worry about them getting cooked in a way. For Propeller II BGA chips, it's easier, you just put an Aluminum / Copper heatsink brick atop the packages as it would usually get rid of heats, either actively or passively.
Tried looking around for some GDDR3 I could pop on the FPGA switcher chip - no luck. (even XDR are not obtainable at most stores, which is no surprise. Still, I would like to use this RAM as it would cut my job out trying to match the traces with rulers, compasses and maybe a thick glass. Alright, I was just joking about the last part.)
Looks like I will have to stick with DDR3, which are pretty much standard by now, and it's a bit pricey - but it's because they're made with smaller lithography geometry - most about 75nm and some even as small as 32nm.
DDR2 may work if DDR3 is not obtainable, though. -___-;
It's best to give yourself some headroom so you won't either melt the insulators off the wires or blow up the power supply (the cheapest SMPS usually explode if it doesn't trip quickly enough - a bit expensive one like the Ultra Modular power supply I have in my computer would just shut down immediately once the overload is noticed). You will still want to use the inverter-based voltage regulator or a LDO with 300 to 1,000 milliamps circuit breaker built-in so you won't cook the P8X32A - something to take into an account (like in the Propeller manual). Lastly, you may have to plug in few wires together for a higher-ampere rail, or best yet, use a thick gauge wire for that kind of current (IDE cable usually can only handle 10A before they overheat - at 20A, you're asking for trouble...)
And, also you would want to put in fan if you want huge number of QFN-44 chips in a cabinet so you won't have to worry about them getting cooked in a way. For Propeller II BGA chips, it's easier, you just put an Aluminum / Copper heatsink brick atop the packages as it would usually get rid of heats, either actively or passively.
Good ideas here. I solved the high amp challenge by dividing up props into partitions of 50. The amperage is closely studied and monitored with an ammeter. With this, I'm able to determine how programs affect draw. Some bench equipment allows you to set the threshold which is what I do. So far, ambient is all that's need for props to remain at room temperature. Originally I was planning for special air conditioning but using these techniques so far, special cooling is not needed. That may change however with the intro of 724 more processors and the enabling of more cogs.
Yeah, I may use a P8X32A or PIC18F for the inverter circuitry in the power supply board for an array board, and it may use some type of voltage throttle to compensate for the current draw (like in the CPU voltage regulator on most motherboard - only the voltage is adjustable via 6-bit votage ID, something that Propeller II won't need, thus permanent at 3.3 and 1.8 Volts DC).
And for each of the array board, composed of both Propeller II and XMOS XS1-G4 chips on separate boards, they will have the current sensor chip from Silicon Labs, the AC current sensor - Si8503-C-IM - the QFN-12 20A current sensor placed before being rectified by the high recovery speed bridge rectifier and smoothed - that way the microcontroller will be able to measure the currents before the voltage starts to sag due to excessive drawing of current - also having the microcontroller in power supply portion has an advantage: it can be informed before the arrays starts to take a punch, that way the current draw would be excepted beforehand.
And, in Dendou Oni case, both favors of array boards will be heatsunk and cooled by 92mm fans to be able to remove the stagnation heats outta the processor die, reducing the whole total package temperature while being under heavy computational load.
Yet, I am wondering which IGBT packages I should go with.... TO-263 (SMD) or TO-247 (thru-hole) concerning the current draw from the SMD common-mode inductor being used as a transformer, with large load at the end after the current sensor / bridge rectifier.
Just to give you an example of digital power supply - this one is for HID lamp ballast: http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en553545 and if anyone asks, "Is it possible for P8X32A to be used in the ballast?" Yes, but is it worth it? (I must admit, it's tempting as I got 150 Watts High-Pressure Sodium bulb laying on the desk. I know few thing: Is it easy? No. Is it possible? Yes. Will it be safe? Depends on the codes. Will it be idiot-proof? Dunno. Will it be worth it? Maybe, if you're intending to run that off the batteries.)
And I know it's classified as a high-voltage inverter, there are also low-voltage ones, such as the one on your ATX motherboard, feeding the power to the CPU chip. What I have on my Gigabyte GA-MA78GM-S2HP motherboard is considerably beefed-up, there are four phases of MOSFETs, inductors, solid-polymer capacitors and diodes connected between 12V plug and the Phenom II Deneb processor - rated for 115 Amps (140W) Maximum.r
Off topic, though, from what I readed from most of Chip Gracey's posts about x1080 picture resolution.
I just got a TV with broken inverter (I will replace few parts, though), now it occurred to me, "if the 180nm SOI Propeller II chip won't be able to toggle the HDMI / DVI quickly enough.... It must be the analog ports that Chip may have been talking about."
See, my Sanyo DP42489 TV can support 1920x1080 resolution via the PC analog RGB port, so it kinda make sense that the Propeller II may have enough tile memory to actually be able to do that.
What about the future die-shrunk ( 90nm SOI ) Propeller II? Maybe, it's possible. If not, then it's down to the 45nm Propeller III chip (which may be likely to have both SOI and Hi-k Metal Gate process, which basically help lengthen the battery life by reducing the transistor leakage substantially).
I have been thinking about the intelligent DC-DC converter... Maybe I should go with PIC as they're dirty cheap, and I won't have to deal with too much bell & whistles, just enough to accomplish the power step-down.
PIC12F629 may be the one I may go with DC-DC converter to properly control the power, stepping down 12V to 1.8V efficiently.
One of the conveniences of lab bench power supply is that you can dial in the voltage across a wide range. Of course you get what you pay for in terms of features like regulation. 1.8 or 3.3, 5 or 12 volts are all selectable along with in between values from 0. There's digital meters to monitor fractional voltage and amperage and controls for fine tuning and ramping. One of these works well with the Propeller I, and over a hundred LEDs and props running at the same time.
Leon, it's what I have been thinking about. Although I wanted to go with something a bit better than with converter chip as the current change's quite unpredictable - like with CPUs, and I wanted something with a bit around 80% efficiency, in the buck conversion hardware soldered on a board.
Humanoido, It's fine if prototyping, but if it has to be buttoned up, it just gets dicey: One mistake or even a glitch, and your 1.8 / 1.2 V processors are cooked. I wanted to put on a permanent PIC-based power supply so it's a bit easier to control what's going on with the entire XS1 transputer and PropII boards, as far as the DC rail is concerned. (and I have used PC power supply as a lab bench SMPS, it worked nicely in term of higher ampere output and weight of overall hardwares).
And, of course, better capacitors are also a must for very sensitive ICs - Nichicon, Sanyo, and Panasonic have quite good low-ESR Aluminum oxide polymer capacitors, and I have been using Nichicon ones, they're pretty much excellent, even in brutal environment such as switchmode power supply - which some liquid electrolytic capacitors just explode, spilling nasty stuff all over the PCB, which you will have to clean up before it starts to eat away at the traces. With this voltage at the rail, I may just need 2.5 Volts, and 100 - 800uF rating to keep Propeller II / XS1 happy.
With lots of benefits of using PIC as an inverter controller, I don't see why not... It got lot of benefits (even in the active Power Factor Corrector, which in some case, complete digital control is required for higher efficiency). They're also found in some LED flashlight (perhaps ICON Rogue II that I also owns).
Well, XS1 wouldn't be a transputer, they were based on Txxx (which got me thinking - XMOS = InMOS), and some VLIW processors on the GPU die are loosely based on the transputer networking concepts. For some reason, I felt like labeling the whole hardware, "XS1 transputer"... Probably I am wrong about the XMOS processors...
And, Heater, you are right about several favors of transputers.
I am wondering about some existing transputers, "Are they now being produced at smaller nodes than 1,500 - 1,200 nanometer n-metal CMOS used to produce the original Txxx chips?", and "are they still in-order and elegantly simple, or due to allowance from smaller lithography node, are they now out-of-order SIMD engines?" I am not sure, but probably few would come across and give me something interesting to read, or just finding out by myself - either way.
XMOS <> INMOS but they were both started by the same guy, David May.
As far as I know the transputer was taken over by STC and was subsequently discontinued.
Have a search for "Transputer History" for some interesting reading.
Get a load of this http://www.cs.bris.ac.uk/~dave/photographs/B0042.jpg
Yep. For some funny reason, it felt like XS1 is a transputer, just by a glance... But it may not be a transputer like Heater pointed out. Maybe it's a Pandora's box, made of Silicon. -____-;
Who knows? I may mess with one soon. (I want to get my hand on T8 series chip just for curiosity. I like computing history too, another reason for having a T8 chip, although they're now harder to find, even on eBay.)
And yea, I recalled reading about InMOS's demise, being killed off by SGS Thomson... They should have continued with it - if they were being improved, it would have been a 7-stage, out-of-order multicore transputer chip which would also be used as a GPU like Radeon.
Using the 64-bit transputer as a basis for x86-64 processor, kinda like what Transmeta did with the VLIW processors, would be interesting too, if it could have been done.
Now, I found few InMOS chips (mounted on a daughter-board) on eBay, they are going to cost me an arm and a leg...
Correct me if I am wrong.... T9000 dieshot looked like this transputer could be designed to be a superscalar processor, by the looks of the main logics (Integer Units, microcode decoderrs, and several vital organs) being arranged that way..... And, I think it's a 800nm die. I found the T9000 dieshot: http://www.inmos.com/images/t9000/index.html
EDIT: Looks like I was right about T9000 being a superscalar transputer: http://www.cbronline.com/news/inmos_previews_its_200_mips_25mhz_superscalar_transputer and http://www.highbeam.com/doc/1G1-13752160.html - too bad ST shot it outta sky, coulda been more useful - if it's still alive and have become more sophisticated, it could have been easily a 7-stage Out-of-Order Execution, maybe 16 - 32 cores SoC transputer which could be also usable by today's PC, helping out with transcoding VCD / DVD / MPEG-2 videos into Blu-ray Disc M2TS files.
I am thinking about buying a XS1 chip this or next month: http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=880-1000-ND so I can play with it for a while so I can make a refined firmware for a full-blown XS1-G4 (or XS1-L4) based boards, along with Propeller II boards, after I figure out what makes it tick.
Still can't wait for some detailed technical documents concerning Propeller II chips so I would get a bit detailed insight on this processor....
(Eh... It was kinda Leon who led me there. Still, it's a pretty good hardware BUT I still got a bone to pick with it: Four cores, and it costs $20 a pop, and look, a $8 microcontroller, Propeller is already octo-core.... Pointing out the demises of Intel Netburst, Hyper-Threading stuff really ensued its painful death: Multi-Threaded processing is never superior as proven in few benchmarks on P4-HT systems - putting in some more cores or if the particular processor's in-order, converting that processor into an out-of-order (probably multi-core) processors are better answer already, like with P8X32A, although this stuff's in-order.)
Yep. Still, like with P8X32A and its successor, that stuff can get quite fast if used right, and the firmware is set up to make sure everything run smooth (I may want to put in emergency bootstrap firmware in OTP just in case that the firmware image on the SPI flash / MRAM gets bricked - that way this chip [I had to respect Heater's request, I won't name it the 3 word...] will be able to still boot up and recover the main (updatable) firmware).
I may decide to put you-know-what on Propeller II board too to be used as IO plane controller after FPGA (IO speed slow-down and conversion and few stuff to go with it - and of course both chip will also provide link to the motherboard) - to ensure that there is no IO crashes. It won't be a definite yes, until I get a REAL GOOD AND LONG looks at the Propeller II datasheets.
Well, to make long story short, I am happy that both microcontrollers are inexpensive and quite powerful, although one of microcontroller I like, Propeller, is the main focus here. On the other forum, that three-word chip. I am not a troll, though - I tend to use mixed hardware if desired or necessary... I do not care if that XYZ or ABC chip is powerful - I just use what I can get my dirty hands on, probably toy with it.
This CPU really impressed me, by the fact that those hardwares were finalized in 1992 and many GPUs were horrible at performing 3D graphic calculation back then - this stuff pulled it off.... O_____O
Comments
The options just rapidly dwindle when confronting with SPIN.... I may write the SPIN JITC (Just-in-Time Compiler), but then it's not going to be easy, starting with the inefficient SPIN emulator already written in the on-die first-stage boot firmware (V 1.0)....
One very infamous "memory wall" - Von Neumann Bottleneck.
Another one, prolongation delay in the wiring.
Yet, I have been thinking about putting in the FPGA in the final revision which will turn out to be the best action to perform, because of Von Neumann bottleneck: The faster the XMOS transputer or Parallax Propeller transfer the data, the bigger the memory wall gets.... Even 8 Propeller II interconnected to a FPGA would outrun the SDRAM cache, thus it just get difficult to keep the Propeller II chips happy while being able to hold down the sustained IO speed. GDDR3 seems to be the best option, the only issue is, not every FPGAs know how to deal with the higher-speed RAM originally designed for video processor hardware.
Another still, the wiring inside the circuit used not to matter much - at least in the older supercomputers, such as the one fitted with InMOS Transputers T414, as the FSB out of those CPUs were of fairly low frequency - about 15MHz. Now, not so simple anymore. We're seeing the AMD Hypertransport pipelines and Intel QuickAssist pipelines approaching 4 GHz, and the RAMs slowly creeping to 2 GHz - the wiring parasitic resistances and trace size starts to matter much more. The only two methods to counter that IO prolongation delay issues are: Trace-matching on PCB designs and / or IO delay training.
And, sorry if I didn't mention any of those words in the PDFs, they're similar to what I wrote in the PDF.
In order to have the best supercomputing experience, I must emphasize again:
1. Take Von Neumann bottleneck between the RAM and processors into account. (You can use SRAM or SDRAM as a cache RAM linked to the processor to help reduce that problem by 1 / 2 or 1/3 - depending on the configuration but for the FPGA being used as a context switch, it is preferred to have at least 256MB higher speed RAMs so that way the FPGA's CPU core don't get overwhelmed.)
2. Ensure that the same firmware codes are used in all of the microcontrollers being placed into the circuit, but assign the ID each into the firmware ROM ID tags, that way the seed processor and the other processors probably on the same circuitry as the particular microcontroller "CPU" being summoned upon, so that way it is known for it to be delivered to the correct chip.
3. Pick and choose. Just pick the best part such as FPGA as possible to match the necessary bandwidth requirement (With 8 P8X32A chips, it is easy. But with eight Propeller II chips, it would become a sort of bandwidth nightmare...)
4. Get the RTOS (FreeRTOS or uCLinux for example) and configure it for preemptive "hook and trunk" callback so that way the necessary numbers of P8X32A can be called into the action in the simple way or your preferred way of requesting the service - at least for some people, Linux is straightforward to be configured. You can always build one from scratch if you prefer.
5. Always be sure you get the strongest Switchmode power supply possible. ATX SMPS are easier to obtain, but you need to be sure, by multiple the worst-case scenario current consumption of an individual processor and multiple by the processors you are going to use - that way you will be able to get what you need what you can offer yourself a headroom. Ex: A P8X32A can have max consumption of 300mA and you want to use 20 or 80 chips. Multiply its consumption by the number of chips = 300mA x 20 chips = 6 Amps (10A headroom recommended) and 300mA x 80 chips = 24 Amps (65 Amps headroom recommended). You gotta give yourself some headroom when dealing with it. And, if you go with switchmode voltage regulator, I would prefer for to go with 12 Volts rail to be regulated down to 3.3 or 1.8 Volts, that way you won't accidentally melt the insulators off the wires.
Note: It is not just for Propeller II based supercomputer hardware, it does apply to every hardware, including the XMOS XS1 transputer based array supercomputer. Even PIC32. You just have to ensure that every little things work first then you can go ahead and pump the data into it - that way you will know it works fine and is stable. Number 5, about an OS, isn't going to matter anyhow, you would still need a way to feed the data into it and receive the results out from the hardware.
Why XS1? It's the nature of the transputers that would lend to when the Propeller II arrays becomes stressed, the XS1 can pick off the GDDR3's content and to reduce the stress - I also noticed on the XCORE forums, they take the punishments pretty reasonable. You can stuff lot of stuff without strangling this chip. I am going to use it as a backup processor - I can choose between CPU type in the menu anyways. That way it's made simple when I am dealing with every environment, even the rapidly-changing ones.
Wow, Dr. Mario, very nice! Your postings are like chapters in a Machine Bible to follow along and gain advice for all good things regarding these projects. It's great that we can apply the technology, methods and results of one chip with others of varying types.
I have found that the maximum amperage draw from Partitions of 50 propeller chips, or 5 in the tester, or over a hundred in the the multiple Partitions can vary significantly. I have been wow'd numerous times with the same circuit, because it went from software A to software B with varying cog work demand, which resulted in massive changes in current draw. The smaller "Brain Child," with five Propellers, could increase from 5ma to 40ma for example just by changing out computational software. I've gone easy on this being careful never to exceed 2 amps in three partitions. But this could change when unleashing the full simultaneous multi-chip computational power. You only need to run some programs that do different levels of processing to observe the effects. This could be a study in itself. I had hoped someone would do the study and give some guidelines about which functions draw what power.
Indeed the Transputer is an amazing machine and literally many genius' worked to design and implement it, and it remains as a great inspiration to all of us today. It's remarkable we can still find elements of the original company. I think we have a lot to learn from the initial waves of paralleled technology for the 40s and 50s and can apply such technology in new ways.
At full bore, at 80 MHz and all 8 cogs running, a Propeller draws about 200 milliamps at 3v3. This doesn't count power dissipated in the I/O circuitry. An overclocked Prop probably draws more and the main reason for the spec being 80 MHz might be that while yes, you can overclock the Prop, if you do and you run full bore on all 8 cogs you might overheat the chip. Max ratings are usually meant to include any abuses you might sneak in and with the 8-cog architecture you have a lot of room to sneak in under the worst case with an abuse.
"What constitutes running" is actually pretty simple. Cogs are always either stopped, running, or waiting. If a cog is doing nothing more computationally intensive than sitting in an infinite JMP #$ PASM loop it will draw the same power as one doing a fourier transform. Cogs in wait states draw much less power, and those not running hardly any.
It's best to give yourself some headroom so you won't either melt the insulators off the wires or blow up the power supply (the cheapest SMPS usually explode if it doesn't trip quickly enough - a bit expensive one like the Ultra Modular power supply I have in my computer would just shut down immediately once the overload is noticed). You will still want to use the inverter-based voltage regulator or a LDO with 300 to 1,000 milliamps circuit breaker built-in so you won't cook the P8X32A - something to take into an account (like in the Propeller manual). Lastly, you may have to plug in few wires together for a higher-ampere rail, or best yet, use a thick gauge wire for that kind of current (IDE cable usually can only handle 10A before they overheat - at 20A, you're asking for trouble...)
And, also you would want to put in fan if you want huge number of QFN-44 chips in a cabinet so you won't have to worry about them getting cooked in a way. For Propeller II BGA chips, it's easier, you just put an Aluminum / Copper heatsink brick atop the packages as it would usually get rid of heats, either actively or passively.
Looks like I will have to stick with DDR3, which are pretty much standard by now, and it's a bit pricey - but it's because they're made with smaller lithography geometry - most about 75nm and some even as small as 32nm.
DDR2 may work if DDR3 is not obtainable, though. -___-;
And for each of the array board, composed of both Propeller II and XMOS XS1-G4 chips on separate boards, they will have the current sensor chip from Silicon Labs, the AC current sensor - Si8503-C-IM - the QFN-12 20A current sensor placed before being rectified by the high recovery speed bridge rectifier and smoothed - that way the microcontroller will be able to measure the currents before the voltage starts to sag due to excessive drawing of current - also having the microcontroller in power supply portion has an advantage: it can be informed before the arrays starts to take a punch, that way the current draw would be excepted beforehand.
And, in Dendou Oni case, both favors of array boards will be heatsunk and cooled by 92mm fans to be able to remove the stagnation heats outta the processor die, reducing the whole total package temperature while being under heavy computational load.
Yet, I am wondering which IGBT packages I should go with.... TO-263 (SMD) or TO-247 (thru-hole) concerning the current draw from the SMD common-mode inductor being used as a transformer, with large load at the end after the current sensor / bridge rectifier.
Just to give you an example of digital power supply - this one is for HID lamp ballast: http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en553545 and if anyone asks, "Is it possible for P8X32A to be used in the ballast?" Yes, but is it worth it? (I must admit, it's tempting as I got 150 Watts High-Pressure Sodium bulb laying on the desk. I know few thing: Is it easy? No. Is it possible? Yes. Will it be safe? Depends on the codes. Will it be idiot-proof? Dunno. Will it be worth it? Maybe, if you're intending to run that off the batteries.)
And I know it's classified as a high-voltage inverter, there are also low-voltage ones, such as the one on your ATX motherboard, feeding the power to the CPU chip. What I have on my Gigabyte GA-MA78GM-S2HP motherboard is considerably beefed-up, there are four phases of MOSFETs, inductors, solid-polymer capacitors and diodes connected between 12V plug and the Phenom II Deneb processor - rated for 115 Amps (140W) Maximum.r
I just got a TV with broken inverter (I will replace few parts, though), now it occurred to me, "if the 180nm SOI Propeller II chip won't be able to toggle the HDMI / DVI quickly enough.... It must be the analog ports that Chip may have been talking about."
See, my Sanyo DP42489 TV can support 1920x1080 resolution via the PC analog RGB port, so it kinda make sense that the Propeller II may have enough tile memory to actually be able to do that.
What about the future die-shrunk ( 90nm SOI ) Propeller II? Maybe, it's possible. If not, then it's down to the 45nm Propeller III chip (which may be likely to have both SOI and Hi-k Metal Gate process, which basically help lengthen the battery life by reducing the transistor leakage substantially).
Just my two cents.
PIC12F629 may be the one I may go with DC-DC converter to properly control the power, stepping down 12V to 1.8V efficiently.
Humanoido, It's fine if prototyping, but if it has to be buttoned up, it just gets dicey: One mistake or even a glitch, and your 1.8 / 1.2 V processors are cooked. I wanted to put on a permanent PIC-based power supply so it's a bit easier to control what's going on with the entire XS1 transputer and PropII boards, as far as the DC rail is concerned. (and I have used PC power supply as a lab bench SMPS, it worked nicely in term of higher ampere output and weight of overall hardwares).
And, of course, better capacitors are also a must for very sensitive ICs - Nichicon, Sanyo, and Panasonic have quite good low-ESR Aluminum oxide polymer capacitors, and I have been using Nichicon ones, they're pretty much excellent, even in brutal environment such as switchmode power supply - which some liquid electrolytic capacitors just explode, spilling nasty stuff all over the PCB, which you will have to clean up before it starts to eat away at the traces. With this voltage at the rail, I may just need 2.5 Volts, and 100 - 800uF rating to keep Propeller II / XS1 happy.
With lots of benefits of using PIC as an inverter controller, I don't see why not... It got lot of benefits (even in the active Power Factor Corrector, which in some case, complete digital control is required for higher efficiency). They're also found in some LED flashlight (perhaps ICON Rogue II that I also owns).
A board may be planned to have eight Propeller II chips - 300mA x 8 = 2.4 A (6.8A peak) so the SMPS has to be a bit beefed up for 16A as the SDRAM chips are also included - along with the SPI magnetic RAMs (either http://www.everspin.com/products.php?hjk=SERIAL&a1f3=4Mb or http://www.everspin.com/products.php?hjk=SERIAL&a1f3=1Mb ) altogether on a board.
There are various types of XS1 chip and there were a variety of Transputers. Despite a lot of ideas in common they are very different devices.
There is no such thing as "XS1 transputer".
And, Heater, you are right about several favors of transputers.
I am wondering about some existing transputers, "Are they now being produced at smaller nodes than 1,500 - 1,200 nanometer n-metal CMOS used to produce the original Txxx chips?", and "are they still in-order and elegantly simple, or due to allowance from smaller lithography node, are they now out-of-order SIMD engines?" I am not sure, but probably few would come across and give me something interesting to read, or just finding out by myself - either way.
As far as I know the transputer was taken over by STC and was subsequently discontinued.
Have a search for "Transputer History" for some interesting reading.
Get a load of this http://www.cs.bris.ac.uk/~dave/photographs/B0042.jpg
Who knows? I may mess with one soon. (I want to get my hand on T8 series chip just for curiosity. I like computing history too, another reason for having a T8 chip, although they're now harder to find, even on eBay.)
And yea, I recalled reading about InMOS's demise, being killed off by SGS Thomson... They should have continued with it - if they were being improved, it would have been a 7-stage, out-of-order multicore transputer chip which would also be used as a GPU like Radeon.
Using the 64-bit transputer as a basis for x86-64 processor, kinda like what Transmeta did with the VLIW processors, would be interesting too, if it could have been done.
Now, I found few InMOS chips (mounted on a daughter-board) on eBay, they are going to cost me an arm and a leg...
EDIT: Looks like I was right about T9000 being a superscalar transputer: http://www.cbronline.com/news/inmos_previews_its_200_mips_25mhz_superscalar_transputer and http://www.highbeam.com/doc/1G1-13752160.html - too bad ST shot it outta sky, coulda been more useful - if it's still alive and have become more sophisticated, it could have been easily a 7-stage Out-of-Order Execution, maybe 16 - 32 cores SoC transputer which could be also usable by today's PC, helping out with transcoding VCD / DVD / MPEG-2 videos into Blu-ray Disc M2TS files.
Still can't wait for some detailed technical documents concerning Propeller II chips so I would get a bit detailed insight on this processor....
(Eh... It was kinda Leon who led me there. Still, it's a pretty good hardware BUT I still got a bone to pick with it: Four cores, and it costs $20 a pop, and look, a $8 microcontroller, Propeller is already octo-core.... Pointing out the demises of Intel Netburst, Hyper-Threading stuff really ensued its painful death: Multi-Threaded processing is never superior as proven in few benchmarks on P4-HT systems - putting in some more cores or if the particular processor's in-order, converting that processor into an out-of-order (probably multi-core) processors are better answer already, like with P8X32A, although this stuff's in-order.)
I may decide to put you-know-what on Propeller II board too to be used as IO plane controller after FPGA (IO speed slow-down and conversion and few stuff to go with it - and of course both chip will also provide link to the motherboard) - to ensure that there is no IO crashes. It won't be a definite yes, until I get a REAL GOOD AND LONG looks at the Propeller II datasheets.
Well, to make long story short, I am happy that both microcontrollers are inexpensive and quite powerful, although one of microcontroller I like, Propeller, is the main focus here. On the other forum, that three-word chip. I am not a troll, though - I tend to use mixed hardware if desired or necessary... I do not care if that XYZ or ABC chip is powerful - I just use what I can get my dirty hands on, probably toy with it.
One video on Youtube shows the capabilities of the InMOS transputer processors: http://www.youtube.com/watch?v=o7byWAv6qCk
This CPU really impressed me, by the fact that those hardwares were finalized in 1992 and many GPUs were horrible at performing 3D graphic calculation back then - this stuff pulled it off.... O_____O