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2-layer PCB ground plane advice — Parallax Forums

2-layer PCB ground plane advice

FlyingFishFingerFlyingFishFinger Posts: 461
edited 2010-09-07 08:50 in General Discussion
Hi-
I'm rather confused on the conventions for ground planes on 2-layer PCB's. I seem to have seen commercial ones that have one on the bottom, and some that don't.
The reason I'm asking is that I've designed a few boards that have mostly been so small / full of traces that there wasn't much leftover space, but this time we've got some that have lots of empty space on them. Is it good practice to cover the bottom and /or top side with a ground plane, and what's a good explanation for why or why not?
Thanks!

Rafael

Comments

  • mctriviamctrivia Posts: 3,772
    edited 2010-09-01 09:53
    The reason for a ground plane is to reduce emi. The farther the return current has to travel from the trace the worse it will be. Ideally on a 2 layer design one side will be all copper ground the other side has all the traces.

    When you send power down a trace on the top the return current will follow the trace on the back side of the board back as much as possible. For this reason if you do run traces on the ground plane side you need to run the trace in a way to minimize how far out of the way the current has to go or create alternate short paths it can use.
  • FlyingFishFingerFlyingFishFinger Posts: 461
    edited 2010-09-01 10:19
    Thanks! I knew the thing about EMI, but I wasn't sure how best to implement on a two-layer. Is it acceptable to have the bottom plane be interrupted by SOME signal lines, or does that entirely defeat its purpose?

    Rafael
  • LeonLeon Posts: 7,620
    edited 2010-09-01 10:23
    Copper areas, even if they are grounded, can cause EMC problems in some circumstances, by acting as antennas. You need to distinguish between true ground and power planes, such as are used on multi-layer PCBs, and copper pour or copper fill, which is often used on simple double-sided PCBs. Good decoupling and layout will help to avoid problems.
  • FlyingFishFingerFlyingFishFinger Posts: 461
    edited 2010-09-01 10:51
    We've got the decoupling, but are you suggesting not to use one? Or is "copper fill" better than no fill on a 2 layer?
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2010-09-01 11:18
    The important thing with a ground pour that contains embedded traces is that it not interrupt or detour any Vss return currents. Once you've finished your board, pull up a view that shows just the Vss connections and the ground pour -- nothing else. Then visually trace where the return currents have to flow to get back to the supply. Isolated areas, of course, would be a fatal problem. But circuitous return paths, even though connected, can be a problem, too. Also, if you have any high-current circuitry, the return paths for those should be direct to the power source and not include other connections to Vss along the way. With proper planning, it's simple to separate these return paths either with traces or with breaks in the ground pour.

    -Phil
  • FlyingFishFingerFlyingFishFinger Posts: 461
    edited 2010-09-01 16:21
    Cool. So is it better to have an unbroken ground plane, at risk of complicating the routing of the other layer or to make routing as direct as possible but having the ground plane interrupted by signal lines?
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2010-09-01 16:33
    On a two-layer board, traces in the ground pour are virtually unavoidable. Just use as few as possible, keep them short, and be smart about how they're routed.

    -Phil
  • mctriviamctrivia Posts: 3,772
    edited 2010-09-01 20:39
    Cool. So is it better to have an unbroken ground plane, at risk of complicating the routing of the other layer or to make routing as direct as possible but having the ground plane interrupted by signal lines?

    As phil said traces on pour are almost unavoidable. there are a few things you can do to reduce the effect of them.



    1) Keep traces on the bottom short and do not cross high frequency signal traces when ever possible.
    2) use a coper pore on both sides of the pcb and use vias to allow return signals to flow for short periods on same side as trace. This can cause ground loops if you are not careful.
    3) use a positive coper pour on side with all traces and use bypass caps to allow return current to travel through positive pour. This increase part count and is strange to understand how it works.
    4) Go to a 4 layer board and use 2 layers just for positive and ground. There are different pools of thought on which layers are best to use for what:

    Some say:
    1) low frequency & secondary traces and parts.
    2) positive plane
    3) ground plane
    4) high frequency & primary traces

    I prefer
    1) positive plane and parts
    2) high frequency and secondary traces
    3) ground plane
    4) low frequency and primary traces

    The advantage of the first is you get a slight decoupling effect between the power planes and the planes will be completely uninterrupted. the disadvantage is the planes are not shielded at all, and traces on the top are far away from the ground plane.

    The advantage of my way is if you route your high frequency traces where there is full copper on the top they are shielded. Also both layers 2 & 4 have great coupling to ground. The disadvantages are boards can be easily rendered useless during rework by pads lifting, and positive plane gets interrupted by parts. It is not a mistake that high frequency and secondary traces are together on my suggestion and high frequency and primary are together in the first option.
  • LoopyBytelooseLoopyByteloose Posts: 12,537
    edited 2010-09-05 12:00
    Those EMI problems were discussed a lot with the SXes as they clocked up to 100Mhz. In general, it was found that clocking at 50Mhz or less eliminated the problems at 5 volts supply. And if you used 3.3 volt supply, you could go much higher.

    It seems that most of the EMI energy is created in the oscillator for the microcontroller. Other signals tend to have less driving force and be less frequent and/or irregular.

    So unless you are doing something with ADC or op-amps, the circuit board is likely to not have problems. But don't forget the de-coupling capacitors at every IC.
  • LeonLeon Posts: 7,620
    edited 2010-09-05 12:44
    It's often the pulse edges that cause problems, rather than the actual clock speed. The issue usually isn't whether the board will work or not, but whether it will meet EMC requirements like those for FCC or CE approval.
  • JavalinJavalin Posts: 892
    edited 2010-09-06 05:12
    i've also done a "split" ground and power plain's arround sensitive components, i.e. gps reciever IC's etc

    See the middle pictures on http://javalins.wordpress.com/projects/databox/

    Seems to work really, really well. Version 1 of the board with a solid gnd layer, version 2 with a split gnd plane results in a faster and better gps lock

    James
  • LoopyBytelooseLoopyByteloose Posts: 12,537
    edited 2010-09-07 08:22
    @Leon
    The reality is that the average hobbyist cannot afford the testing to get a board properly certified as good for EMC requirements. It takes having a shielded room that can measure exactly what is occuring.

    The SXes really can go up to 80Mhz at 5 volts, but beyond that it becomes difficult to prevent without spending big bucks on testing. With the BasicStamp, the SXes, and the Propeller, there is usually no issue unless one is seriously overclocking.

    It doesn't hurt to try to build a board to be reasonably protected, but it is all guess wirk when done without testing. And, the reason for boards with many internal layers is to overcome what a two-layer board cannot really accomplish. Still, it is good to discuss how to get started with it as some people here may eventually end up in engineering and want to get started with thinking about it.
  • LeonLeon Posts: 7,620
    edited 2010-09-07 08:50
    It doesn't matter for hobbyists, but anyone selling products in most countries needs to demonstrate conformity with EMC standards.
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