Start by getting a platform like a demoboard and do the blink-LED's tutorial to learn Spin. The Propeller is so different from other CPU's it's actually very hard to evaluate a question like "what dev environment is better" if you don't have some familiarity with it. The Prop is an ongoing lesson in compromises vis-a-vis speed, memory efficiency, pin usage, and so on. There is an ever-growing list of currently IIRC around 100 languages / dev platforms for the Prop, but you won't be able to make sense of any of them if you don't know the basics of how the Prop boots to Spin code and PASM is used to implement it all.
Yes indeed they do. They also have a shed load of complicated addressing modes to go with them and quite often odd limitations on what registers you can uses as indexes, pointers whatever. Get's worse when it's not just "mov" but "add" or such, then you find out what regs can be used for what ops or not.
I can't think of one processor that has such regular instruction set as the Prop. I believe they use the word "orthogonal" when talking about such things.
I think the Prop is beautiful in this way. It's PASM is the very core of what's needed in a CPU, and it's perfectly executed.
The lack of modes is different, and it gives the perception of the CPU being slow, or limited, but what I've found is those CPUs that do have lots of modes, also consume lots of cycles. This kind of balances out on both speed and code size. Conditional execution on the prop can really cut overall code size down, where on those other CPUs the loading of registers, and branching to do logic tends to bloat it.
It helps that when Programing within COG you have no registers. Only memory for code and data. Wait a minute is that the other way around, you have no memory only registers)
See, "orthogonal".
I think my ideal processor would be a Propeller with 64 bit COGs.
Having 64 bit data and instructions would mean the address fields could be extended from 9 bits to 25 bits. That is each instruction could address 32 mega LONGs !!!
So the 64 bit Prop could have much bigger COG memory space. Perhaps skip the HUB RAM altogether and just have some high speed communication between COGs.
Heater, what's wrong with a little indirect addressing . They were the bane of my existance when learning 6502 Assembly in college.
USMInfinity, I agree with Heater. PASM is about the easiest and will give you a foundation on the basics of assembly if you want to move to another micro-controller or microprocessor
USMCinfinity, Don't worry. PASM is about the easiest assembly language you could wish for.
You think "A := B"
You write "mov A, B
You think "A := A + B"
You write "add A, B"
You think if "A == 3 GOTO somewhere"
You write:
cmp A, #3 wz
if_z jmp #somewhere
And so it goes.
Heater, you could write the book on "Easy PASM!" I want both your books, including "Easy Spin." BTW, who are the authors of the current Easy Spin books? I use PEK and the Propeller manual plus the getting started stickies, and need more.
Many ARM instructions can be executed conditionally by postfixing them with a condition:
ADD r0,r1,r2 is the standard ADD instruction - r0 <- r1+r2
ADDEQ r0,r1,r2 is only executed if the zero flag is set.
This gives very dense, fast code.
Another processor has instructions like LDAWBI (load address of word backward) which uses the operand registers as a base address and combines it with a scaled offset, for efficient access to data structures.
Those chips, and many others, can also perform a MAC (multiply and accumulate) operation in one instruction, which speeds up signal processing applications, although they aren't DSPs.
With a 32-bit architecture it's quite easy to add stuff like that.
Comments
If you are, this may get you started. Lots of info here.
http://forums.parallax.com/showthread.php?t=113091&highlight=list+programming+languages
hope this helps.
I think that the free Catalina C compiler and the free
PropBASIC compilers are great :-)
Don't worry. PASM is about the easiest assembly language you could wish for.
You think "A := B"
You write "mov A, B
You think "A := A + B"
You write "add A, B"
You think if "A == 3 GOTO somewhere"
You write:
And so it goes.
Yes indeed they do. They also have a shed load of complicated addressing modes to go with them and quite often odd limitations on what registers you can uses as indexes, pointers whatever. Get's worse when it's not just "mov" but "add" or such, then you find out what regs can be used for what ops or not.
I can't think of one processor that has such regular instruction set as the Prop. I believe they use the word "orthogonal" when talking about such things.
Macros give me headache:)
I think the Prop is beautiful in this way. It's PASM is the very core of what's needed in a CPU, and it's perfectly executed.
The lack of modes is different, and it gives the perception of the CPU being slow, or limited, but what I've found is those CPUs that do have lots of modes, also consume lots of cycles. This kind of balances out on both speed and code size. Conditional execution on the prop can really cut overall code size down, where on those other CPUs the loading of registers, and branching to do logic tends to bloat it.
Overall it's a good trade off.
See, "orthogonal".
I think my ideal processor would be a Propeller with 64 bit COGs.
Having 64 bit data and instructions would mean the address fields could be extended from 9 bits to 25 bits. That is each instruction could address 32 mega LONGs !!!
So the 64 bit Prop could have much bigger COG memory space. Perhaps skip the HUB RAM altogether and just have some high speed communication between COGs.
USMInfinity, I agree with Heater. PASM is about the easiest and will give you a foundation on the basics of assembly if you want to move to another micro-controller or microprocessor
Humanoido
Yeah? ....... Which ones Leon?
ADD r0,r1,r2 is the standard ADD instruction - r0 <- r1+r2
ADDEQ r0,r1,r2 is only executed if the zero flag is set.
This gives very dense, fast code.
Another processor has instructions like LDAWBI (load address of word backward) which uses the operand registers as a base address and combines it with a scaled offset, for efficient access to data structures.
Those chips, and many others, can also perform a MAC (multiply and accumulate) operation in one instruction, which speeds up signal processing applications, although they aren't DSPs.
With a 32-bit architecture it's quite easy to add stuff like that.