Interfacing to a 1Kz signal - advice please
pacman
Posts: 327
I'm not even where to start - Can someone start me on my way please
I have a 2 wire signal that has a 1kHz square pulse train on it (every 128mS there is a 8mS wide pulse to enable syncing, so in 'reality" it is not quite 1kHz).
The prop will need to watch the the signal, wait for the 8mS sync pulse an start counting. If in the the first 250uS of the pulse is value is low the 'bit' is off, if it isn't then the 'bit' is high - The nest 250uS can be either high or low, and the last 500uS will be high. Each mS represents another data bit
This signal has a _typical_ high section of the pulse of around 9V (but it could be as high as 14V, and as low as 6V), anything below 2.2V is considered OFF.
I need to interface to this signal without distorting the original. Given the potentially wideish input voltages - can someone recommend some appropriate interface circuit/chips to use. Even getting a hint as to the family of chip to use would be a great start.
My limited knowledge suggests that I would need a high impedance input circuit (so as to not load the signal line) - but I really have no clue (even more than usual) on this this.
thanks in advance
I have a 2 wire signal that has a 1kHz square pulse train on it (every 128mS there is a 8mS wide pulse to enable syncing, so in 'reality" it is not quite 1kHz).
The prop will need to watch the the signal, wait for the 8mS sync pulse an start counting. If in the the first 250uS of the pulse is value is low the 'bit' is off, if it isn't then the 'bit' is high - The nest 250uS can be either high or low, and the last 500uS will be high. Each mS represents another data bit
This signal has a _typical_ high section of the pulse of around 9V (but it could be as high as 14V, and as low as 6V), anything below 2.2V is considered OFF.
I need to interface to this signal without distorting the original. Given the potentially wideish input voltages - can someone recommend some appropriate interface circuit/chips to use. Even getting a hint as to the family of chip to use would be a great start.
My limited knowledge suggests that I would need a high impedance input circuit (so as to not load the signal line) - but I really have no clue (even more than usual) on this this.
thanks in advance
Comments
1. lower the input voltage, so 2.2V input matches the prop logical threshold (1.65V at 3.3V power)
2. Protect the prop from high input voltage.
The first can be achieved by a simple voltage divider, the second with a limiting resistor. The schematic is attached. Choose R1 and R2 depending on input impedance required, keeping R1/R2 ratio 1/3. R3 is chosen big enough to not exceed prop's internal clamping diodes current limit. Specified limit is 500 uA, and 22k resistor should be enough.
And like so many things in life, the answer was simple...
So Thanks again
Andy
You could then use WAITCNT to wait 125us to the middle of the first part of the data and check whether the signal is low or high (0 or 1). You can use WAITCNT again to wait 1ms to the middle of the next data bit and repeat until you get all the data bits. At the end, you'd start over again looking for a sync pulse.
I must be getting better at this..This is what I was thinking of doing - I even have some 'sample' code that compiles that tries to do this (haven't actually got it onto a Prop board yet as I'm 100's of Ks away from home base ATM). So the code might compile but actually NOT do the intent..
Code is attached but DON'T devote too much time to examining it - as it is still very much a work in progress. Though if you do want something to have a giggle about - then go ahead. All constructive criticism welcome